1#[doc = "Register `cci_cfg` reader"]
2pub struct R(crate::R<CCI_CFG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CCI_CFG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CCI_CFG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CCI_CFG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `cci_cfg` writer"]
17pub struct W(crate::W<CCI_CFG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CCI_CFG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CCI_CFG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CCI_CFG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `cci_en` reader - "]
38pub type CCI_EN_R = crate::BitReader<bool>;
39#[doc = "Field `cci_en` writer - "]
40pub type CCI_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
41#[doc = "Field `cci_slv_sel_cci2` reader - "]
42pub type CCI_SLV_SEL_CCI2_R = crate::BitReader<bool>;
43#[doc = "Field `cci_slv_sel_cci2` writer - "]
44pub type CCI_SLV_SEL_CCI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
45#[doc = "Field `cci_mas_sel_cci2` reader - "]
46pub type CCI_MAS_SEL_CCI2_R = crate::BitReader<bool>;
47#[doc = "Field `cci_mas_sel_cci2` writer - "]
48pub type CCI_MAS_SEL_CCI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
49#[doc = "Field `cci_mas_hw_mode` reader - "]
50pub type CCI_MAS_HW_MODE_R = crate::BitReader<bool>;
51#[doc = "Field `cci_mas_hw_mode` writer - "]
52pub type CCI_MAS_HW_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
53#[doc = "Field `reg_m_cci_sclk_en` reader - "]
54pub type REG_M_CCI_SCLK_EN_R = crate::BitReader<bool>;
55#[doc = "Field `reg_m_cci_sclk_en` writer - "]
56pub type REG_M_CCI_SCLK_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
57#[doc = "Field `reg_div_m_cci_sclk` reader - "]
58pub type REG_DIV_M_CCI_SCLK_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `reg_div_m_cci_sclk` writer - "]
60pub type REG_DIV_M_CCI_SCLK_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, CCI_CFG_SPEC, u8, u8, 2, O>;
62#[doc = "Field `cfg_cci1_pre_read` reader - "]
63pub type CFG_CCI1_PRE_READ_R = crate::BitReader<bool>;
64#[doc = "Field `cfg_cci1_pre_read` writer - "]
65pub type CFG_CCI1_PRE_READ_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
66#[doc = "Field `reg_scci_clk_inv` reader - "]
67pub type REG_SCCI_CLK_INV_R = crate::BitReader<bool>;
68#[doc = "Field `reg_scci_clk_inv` writer - "]
69pub type REG_SCCI_CLK_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
70#[doc = "Field `reg_mcci_clk_inv` reader - "]
71pub type REG_MCCI_CLK_INV_R = crate::BitReader<bool>;
72#[doc = "Field `reg_mcci_clk_inv` writer - "]
73pub type REG_MCCI_CLK_INV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CCI_CFG_SPEC, bool, O>;
74impl R {
75 #[doc = "Bit 0"]
76 #[inline(always)]
77 pub fn cci_en(&self) -> CCI_EN_R {
78 CCI_EN_R::new((self.bits & 1) != 0)
79 }
80 #[doc = "Bit 1"]
81 #[inline(always)]
82 pub fn cci_slv_sel_cci2(&self) -> CCI_SLV_SEL_CCI2_R {
83 CCI_SLV_SEL_CCI2_R::new(((self.bits >> 1) & 1) != 0)
84 }
85 #[doc = "Bit 2"]
86 #[inline(always)]
87 pub fn cci_mas_sel_cci2(&self) -> CCI_MAS_SEL_CCI2_R {
88 CCI_MAS_SEL_CCI2_R::new(((self.bits >> 2) & 1) != 0)
89 }
90 #[doc = "Bit 3"]
91 #[inline(always)]
92 pub fn cci_mas_hw_mode(&self) -> CCI_MAS_HW_MODE_R {
93 CCI_MAS_HW_MODE_R::new(((self.bits >> 3) & 1) != 0)
94 }
95 #[doc = "Bit 4"]
96 #[inline(always)]
97 pub fn reg_m_cci_sclk_en(&self) -> REG_M_CCI_SCLK_EN_R {
98 REG_M_CCI_SCLK_EN_R::new(((self.bits >> 4) & 1) != 0)
99 }
100 #[doc = "Bits 5:6"]
101 #[inline(always)]
102 pub fn reg_div_m_cci_sclk(&self) -> REG_DIV_M_CCI_SCLK_R {
103 REG_DIV_M_CCI_SCLK_R::new(((self.bits >> 5) & 3) as u8)
104 }
105 #[doc = "Bit 7"]
106 #[inline(always)]
107 pub fn cfg_cci1_pre_read(&self) -> CFG_CCI1_PRE_READ_R {
108 CFG_CCI1_PRE_READ_R::new(((self.bits >> 7) & 1) != 0)
109 }
110 #[doc = "Bit 8"]
111 #[inline(always)]
112 pub fn reg_scci_clk_inv(&self) -> REG_SCCI_CLK_INV_R {
113 REG_SCCI_CLK_INV_R::new(((self.bits >> 8) & 1) != 0)
114 }
115 #[doc = "Bit 9"]
116 #[inline(always)]
117 pub fn reg_mcci_clk_inv(&self) -> REG_MCCI_CLK_INV_R {
118 REG_MCCI_CLK_INV_R::new(((self.bits >> 9) & 1) != 0)
119 }
120}
121impl W {
122 #[doc = "Bit 0"]
123 #[inline(always)]
124 #[must_use]
125 pub fn cci_en(&mut self) -> CCI_EN_W<0> {
126 CCI_EN_W::new(self)
127 }
128 #[doc = "Bit 1"]
129 #[inline(always)]
130 #[must_use]
131 pub fn cci_slv_sel_cci2(&mut self) -> CCI_SLV_SEL_CCI2_W<1> {
132 CCI_SLV_SEL_CCI2_W::new(self)
133 }
134 #[doc = "Bit 2"]
135 #[inline(always)]
136 #[must_use]
137 pub fn cci_mas_sel_cci2(&mut self) -> CCI_MAS_SEL_CCI2_W<2> {
138 CCI_MAS_SEL_CCI2_W::new(self)
139 }
140 #[doc = "Bit 3"]
141 #[inline(always)]
142 #[must_use]
143 pub fn cci_mas_hw_mode(&mut self) -> CCI_MAS_HW_MODE_W<3> {
144 CCI_MAS_HW_MODE_W::new(self)
145 }
146 #[doc = "Bit 4"]
147 #[inline(always)]
148 #[must_use]
149 pub fn reg_m_cci_sclk_en(&mut self) -> REG_M_CCI_SCLK_EN_W<4> {
150 REG_M_CCI_SCLK_EN_W::new(self)
151 }
152 #[doc = "Bits 5:6"]
153 #[inline(always)]
154 #[must_use]
155 pub fn reg_div_m_cci_sclk(&mut self) -> REG_DIV_M_CCI_SCLK_W<5> {
156 REG_DIV_M_CCI_SCLK_W::new(self)
157 }
158 #[doc = "Bit 7"]
159 #[inline(always)]
160 #[must_use]
161 pub fn cfg_cci1_pre_read(&mut self) -> CFG_CCI1_PRE_READ_W<7> {
162 CFG_CCI1_PRE_READ_W::new(self)
163 }
164 #[doc = "Bit 8"]
165 #[inline(always)]
166 #[must_use]
167 pub fn reg_scci_clk_inv(&mut self) -> REG_SCCI_CLK_INV_W<8> {
168 REG_SCCI_CLK_INV_W::new(self)
169 }
170 #[doc = "Bit 9"]
171 #[inline(always)]
172 #[must_use]
173 pub fn reg_mcci_clk_inv(&mut self) -> REG_MCCI_CLK_INV_W<9> {
174 REG_MCCI_CLK_INV_W::new(self)
175 }
176 #[doc = "Writes raw bits to the register."]
177 #[inline(always)]
178 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
179 self.0.bits(bits);
180 self
181 }
182}
183#[doc = "cci_cfg.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cci_cfg](index.html) module"]
184pub struct CCI_CFG_SPEC;
185impl crate::RegisterSpec for CCI_CFG_SPEC {
186 type Ux = u32;
187}
188#[doc = "`read()` method returns [cci_cfg::R](R) reader structure"]
189impl crate::Readable for CCI_CFG_SPEC {
190 type Reader = R;
191}
192#[doc = "`write(|w| ..)` method takes [cci_cfg::W](W) writer structure"]
193impl crate::Writable for CCI_CFG_SPEC {
194 type Writer = W;
195 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
196 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
197}
198#[doc = "`reset()` method sets cci_cfg to value 0"]
199impl crate::Resettable for CCI_CFG_SPEC {
200 const RESET_VALUE: Self::Ux = 0;
201}