bl702_pac/cam/
int_control.rs

1#[doc = "Register `int_control` reader"]
2pub struct R(crate::R<INT_CONTROL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INT_CONTROL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INT_CONTROL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INT_CONTROL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `int_control` writer"]
17pub struct W(crate::W<INT_CONTROL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INT_CONTROL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INT_CONTROL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INT_CONTROL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `reg_int_normal_0_en` reader - "]
38pub type REG_INT_NORMAL_0_EN_R = crate::BitReader<bool>;
39#[doc = "Field `reg_int_normal_0_en` writer - "]
40pub type REG_INT_NORMAL_0_EN_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
42#[doc = "Field `reg_int_normal_1_en` reader - "]
43pub type REG_INT_NORMAL_1_EN_R = crate::BitReader<bool>;
44#[doc = "Field `reg_int_normal_1_en` writer - "]
45pub type REG_INT_NORMAL_1_EN_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
47#[doc = "Field `reg_int_mem_en` reader - "]
48pub type REG_INT_MEM_EN_R = crate::BitReader<bool>;
49#[doc = "Field `reg_int_mem_en` writer - "]
50pub type REG_INT_MEM_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
51#[doc = "Field `reg_int_frame_en` reader - "]
52pub type REG_INT_FRAME_EN_R = crate::BitReader<bool>;
53#[doc = "Field `reg_int_frame_en` writer - "]
54pub type REG_INT_FRAME_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
55#[doc = "Field `reg_int_fifo_en` reader - "]
56pub type REG_INT_FIFO_EN_R = crate::BitReader<bool>;
57#[doc = "Field `reg_int_fifo_en` writer - "]
58pub type REG_INT_FIFO_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
59#[doc = "Field `reg_int_hcnt_en` reader - "]
60pub type REG_INT_HCNT_EN_R = crate::BitReader<bool>;
61#[doc = "Field `reg_int_hcnt_en` writer - "]
62pub type REG_INT_HCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
63#[doc = "Field `reg_int_vcnt_en` reader - "]
64pub type REG_INT_VCNT_EN_R = crate::BitReader<bool>;
65#[doc = "Field `reg_int_vcnt_en` writer - "]
66pub type REG_INT_VCNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, INT_CONTROL_SPEC, bool, O>;
67#[doc = "Field `reg_frame_cnt_trgr_int` reader - "]
68pub type REG_FRAME_CNT_TRGR_INT_R = crate::FieldReader<u8, u8>;
69#[doc = "Field `reg_frame_cnt_trgr_int` writer - "]
70pub type REG_FRAME_CNT_TRGR_INT_W<'a, const O: u8> =
71    crate::FieldWriter<'a, u32, INT_CONTROL_SPEC, u8, u8, 4, O>;
72impl R {
73    #[doc = "Bit 0"]
74    #[inline(always)]
75    pub fn reg_int_normal_0_en(&self) -> REG_INT_NORMAL_0_EN_R {
76        REG_INT_NORMAL_0_EN_R::new((self.bits & 1) != 0)
77    }
78    #[doc = "Bit 1"]
79    #[inline(always)]
80    pub fn reg_int_normal_1_en(&self) -> REG_INT_NORMAL_1_EN_R {
81        REG_INT_NORMAL_1_EN_R::new(((self.bits >> 1) & 1) != 0)
82    }
83    #[doc = "Bit 2"]
84    #[inline(always)]
85    pub fn reg_int_mem_en(&self) -> REG_INT_MEM_EN_R {
86        REG_INT_MEM_EN_R::new(((self.bits >> 2) & 1) != 0)
87    }
88    #[doc = "Bit 3"]
89    #[inline(always)]
90    pub fn reg_int_frame_en(&self) -> REG_INT_FRAME_EN_R {
91        REG_INT_FRAME_EN_R::new(((self.bits >> 3) & 1) != 0)
92    }
93    #[doc = "Bit 4"]
94    #[inline(always)]
95    pub fn reg_int_fifo_en(&self) -> REG_INT_FIFO_EN_R {
96        REG_INT_FIFO_EN_R::new(((self.bits >> 4) & 1) != 0)
97    }
98    #[doc = "Bit 5"]
99    #[inline(always)]
100    pub fn reg_int_hcnt_en(&self) -> REG_INT_HCNT_EN_R {
101        REG_INT_HCNT_EN_R::new(((self.bits >> 5) & 1) != 0)
102    }
103    #[doc = "Bit 6"]
104    #[inline(always)]
105    pub fn reg_int_vcnt_en(&self) -> REG_INT_VCNT_EN_R {
106        REG_INT_VCNT_EN_R::new(((self.bits >> 6) & 1) != 0)
107    }
108    #[doc = "Bits 28:31"]
109    #[inline(always)]
110    pub fn reg_frame_cnt_trgr_int(&self) -> REG_FRAME_CNT_TRGR_INT_R {
111        REG_FRAME_CNT_TRGR_INT_R::new(((self.bits >> 28) & 0x0f) as u8)
112    }
113}
114impl W {
115    #[doc = "Bit 0"]
116    #[inline(always)]
117    #[must_use]
118    pub fn reg_int_normal_0_en(&mut self) -> REG_INT_NORMAL_0_EN_W<0> {
119        REG_INT_NORMAL_0_EN_W::new(self)
120    }
121    #[doc = "Bit 1"]
122    #[inline(always)]
123    #[must_use]
124    pub fn reg_int_normal_1_en(&mut self) -> REG_INT_NORMAL_1_EN_W<1> {
125        REG_INT_NORMAL_1_EN_W::new(self)
126    }
127    #[doc = "Bit 2"]
128    #[inline(always)]
129    #[must_use]
130    pub fn reg_int_mem_en(&mut self) -> REG_INT_MEM_EN_W<2> {
131        REG_INT_MEM_EN_W::new(self)
132    }
133    #[doc = "Bit 3"]
134    #[inline(always)]
135    #[must_use]
136    pub fn reg_int_frame_en(&mut self) -> REG_INT_FRAME_EN_W<3> {
137        REG_INT_FRAME_EN_W::new(self)
138    }
139    #[doc = "Bit 4"]
140    #[inline(always)]
141    #[must_use]
142    pub fn reg_int_fifo_en(&mut self) -> REG_INT_FIFO_EN_W<4> {
143        REG_INT_FIFO_EN_W::new(self)
144    }
145    #[doc = "Bit 5"]
146    #[inline(always)]
147    #[must_use]
148    pub fn reg_int_hcnt_en(&mut self) -> REG_INT_HCNT_EN_W<5> {
149        REG_INT_HCNT_EN_W::new(self)
150    }
151    #[doc = "Bit 6"]
152    #[inline(always)]
153    #[must_use]
154    pub fn reg_int_vcnt_en(&mut self) -> REG_INT_VCNT_EN_W<6> {
155        REG_INT_VCNT_EN_W::new(self)
156    }
157    #[doc = "Bits 28:31"]
158    #[inline(always)]
159    #[must_use]
160    pub fn reg_frame_cnt_trgr_int(&mut self) -> REG_FRAME_CNT_TRGR_INT_W<28> {
161        REG_FRAME_CNT_TRGR_INT_W::new(self)
162    }
163    #[doc = "Writes raw bits to the register."]
164    #[inline(always)]
165    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
166        self.0.bits(bits);
167        self
168    }
169}
170#[doc = "int_control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [int_control](index.html) module"]
171pub struct INT_CONTROL_SPEC;
172impl crate::RegisterSpec for INT_CONTROL_SPEC {
173    type Ux = u32;
174}
175#[doc = "`read()` method returns [int_control::R](R) reader structure"]
176impl crate::Readable for INT_CONTROL_SPEC {
177    type Reader = R;
178}
179#[doc = "`write(|w| ..)` method takes [int_control::W](W) writer structure"]
180impl crate::Writable for INT_CONTROL_SPEC {
181    type Writer = W;
182    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
183    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
184}
185#[doc = "`reset()` method sets int_control to value 0"]
186impl crate::Resettable for INT_CONTROL_SPEC {
187    const RESET_VALUE: Self::Ux = 0;
188}
bl702_pac/cam/int_control.rs

bl702_pac/cam/
int_control.rs
