1#[doc = "Register `dvp_status_and_error` reader"]
2pub struct R(crate::R<DVP_STATUS_AND_ERROR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DVP_STATUS_AND_ERROR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DVP_STATUS_AND_ERROR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DVP_STATUS_AND_ERROR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `dvp_status_and_error` writer"]
17pub struct W(crate::W<DVP_STATUS_AND_ERROR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DVP_STATUS_AND_ERROR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DVP_STATUS_AND_ERROR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DVP_STATUS_AND_ERROR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `sts_normal_int_0` reader - "]
38pub type STS_NORMAL_INT_0_R = crate::BitReader<bool>;
39#[doc = "Field `sts_normal_int_0` writer - "]
40pub type STS_NORMAL_INT_0_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
42#[doc = "Field `sts_normal_int_1` reader - "]
43pub type STS_NORMAL_INT_1_R = crate::BitReader<bool>;
44#[doc = "Field `sts_normal_int_1` writer - "]
45pub type STS_NORMAL_INT_1_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
47#[doc = "Field `sts_mem_int_0` reader - "]
48pub type STS_MEM_INT_0_R = crate::BitReader<bool>;
49#[doc = "Field `sts_mem_int_0` writer - "]
50pub type STS_MEM_INT_0_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
52#[doc = "Field `sts_mem_int_1` reader - "]
53pub type STS_MEM_INT_1_R = crate::BitReader<bool>;
54#[doc = "Field `sts_mem_int_1` writer - "]
55pub type STS_MEM_INT_1_W<'a, const O: u8> =
56 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
57#[doc = "Field `sts_frame_int_0` reader - "]
58pub type STS_FRAME_INT_0_R = crate::BitReader<bool>;
59#[doc = "Field `sts_frame_int_0` writer - "]
60pub type STS_FRAME_INT_0_W<'a, const O: u8> =
61 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
62#[doc = "Field `sts_frame_int_1` reader - "]
63pub type STS_FRAME_INT_1_R = crate::BitReader<bool>;
64#[doc = "Field `sts_frame_int_1` writer - "]
65pub type STS_FRAME_INT_1_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
67#[doc = "Field `sts_fifo_int_0` reader - "]
68pub type STS_FIFO_INT_0_R = crate::BitReader<bool>;
69#[doc = "Field `sts_fifo_int_0` writer - "]
70pub type STS_FIFO_INT_0_W<'a, const O: u8> =
71 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
72#[doc = "Field `sts_fifo_int_1` reader - "]
73pub type STS_FIFO_INT_1_R = crate::BitReader<bool>;
74#[doc = "Field `sts_fifo_int_1` writer - "]
75pub type STS_FIFO_INT_1_W<'a, const O: u8> =
76 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
77#[doc = "Field `sts_hcnt_int` reader - "]
78pub type STS_HCNT_INT_R = crate::BitReader<bool>;
79#[doc = "Field `sts_hcnt_int` writer - "]
80pub type STS_HCNT_INT_W<'a, const O: u8> =
81 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
82#[doc = "Field `sts_vcnt_int` reader - "]
83pub type STS_VCNT_INT_R = crate::BitReader<bool>;
84#[doc = "Field `sts_vcnt_int` writer - "]
85pub type STS_VCNT_INT_W<'a, const O: u8> =
86 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
87#[doc = "Field `ahb_idle_0` reader - "]
88pub type AHB_IDLE_0_R = crate::BitReader<bool>;
89#[doc = "Field `ahb_idle_0` writer - "]
90pub type AHB_IDLE_0_W<'a, const O: u8> =
91 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
92#[doc = "Field `ahb_idle_1` reader - "]
93pub type AHB_IDLE_1_R = crate::BitReader<bool>;
94#[doc = "Field `ahb_idle_1` writer - "]
95pub type AHB_IDLE_1_W<'a, const O: u8> =
96 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
97#[doc = "Field `st_dvp_idle` reader - "]
98pub type ST_DVP_IDLE_R = crate::BitReader<bool>;
99#[doc = "Field `st_dvp_idle` writer - "]
100pub type ST_DVP_IDLE_W<'a, const O: u8> =
101 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
102#[doc = "Field `frame_valid_cnt_0` reader - "]
103pub type FRAME_VALID_CNT_0_R = crate::FieldReader<u8, u8>;
104#[doc = "Field `frame_valid_cnt_0` writer - "]
105pub type FRAME_VALID_CNT_0_W<'a, const O: u8> =
106 crate::FieldWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, u8, u8, 4, O>;
107#[doc = "Field `frame_valid_cnt_1` reader - "]
108pub type FRAME_VALID_CNT_1_R = crate::FieldReader<u8, u8>;
109#[doc = "Field `frame_valid_cnt_1` writer - "]
110pub type FRAME_VALID_CNT_1_W<'a, const O: u8> =
111 crate::FieldWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, u8, u8, 4, O>;
112#[doc = "Field `st_bus_idle` reader - "]
113pub type ST_BUS_IDLE_R = crate::BitReader<bool>;
114#[doc = "Field `st_bus_idle` writer - "]
115pub type ST_BUS_IDLE_W<'a, const O: u8> =
116 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
117#[doc = "Field `st_bus_func` reader - "]
118pub type ST_BUS_FUNC_R = crate::BitReader<bool>;
119#[doc = "Field `st_bus_func` writer - "]
120pub type ST_BUS_FUNC_W<'a, const O: u8> =
121 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
122#[doc = "Field `st_bus_wait` reader - "]
123pub type ST_BUS_WAIT_R = crate::BitReader<bool>;
124#[doc = "Field `st_bus_wait` writer - "]
125pub type ST_BUS_WAIT_W<'a, const O: u8> =
126 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
127#[doc = "Field `st_bus_flsh` reader - "]
128pub type ST_BUS_FLSH_R = crate::BitReader<bool>;
129#[doc = "Field `st_bus_flsh` writer - "]
130pub type ST_BUS_FLSH_W<'a, const O: u8> =
131 crate::BitWriter<'a, u32, DVP_STATUS_AND_ERROR_SPEC, bool, O>;
132impl R {
133 #[doc = "Bit 0"]
134 #[inline(always)]
135 pub fn sts_normal_int_0(&self) -> STS_NORMAL_INT_0_R {
136 STS_NORMAL_INT_0_R::new((self.bits & 1) != 0)
137 }
138 #[doc = "Bit 1"]
139 #[inline(always)]
140 pub fn sts_normal_int_1(&self) -> STS_NORMAL_INT_1_R {
141 STS_NORMAL_INT_1_R::new(((self.bits >> 1) & 1) != 0)
142 }
143 #[doc = "Bit 2"]
144 #[inline(always)]
145 pub fn sts_mem_int_0(&self) -> STS_MEM_INT_0_R {
146 STS_MEM_INT_0_R::new(((self.bits >> 2) & 1) != 0)
147 }
148 #[doc = "Bit 3"]
149 #[inline(always)]
150 pub fn sts_mem_int_1(&self) -> STS_MEM_INT_1_R {
151 STS_MEM_INT_1_R::new(((self.bits >> 3) & 1) != 0)
152 }
153 #[doc = "Bit 4"]
154 #[inline(always)]
155 pub fn sts_frame_int_0(&self) -> STS_FRAME_INT_0_R {
156 STS_FRAME_INT_0_R::new(((self.bits >> 4) & 1) != 0)
157 }
158 #[doc = "Bit 5"]
159 #[inline(always)]
160 pub fn sts_frame_int_1(&self) -> STS_FRAME_INT_1_R {
161 STS_FRAME_INT_1_R::new(((self.bits >> 5) & 1) != 0)
162 }
163 #[doc = "Bit 6"]
164 #[inline(always)]
165 pub fn sts_fifo_int_0(&self) -> STS_FIFO_INT_0_R {
166 STS_FIFO_INT_0_R::new(((self.bits >> 6) & 1) != 0)
167 }
168 #[doc = "Bit 7"]
169 #[inline(always)]
170 pub fn sts_fifo_int_1(&self) -> STS_FIFO_INT_1_R {
171 STS_FIFO_INT_1_R::new(((self.bits >> 7) & 1) != 0)
172 }
173 #[doc = "Bit 8"]
174 #[inline(always)]
175 pub fn sts_hcnt_int(&self) -> STS_HCNT_INT_R {
176 STS_HCNT_INT_R::new(((self.bits >> 8) & 1) != 0)
177 }
178 #[doc = "Bit 9"]
179 #[inline(always)]
180 pub fn sts_vcnt_int(&self) -> STS_VCNT_INT_R {
181 STS_VCNT_INT_R::new(((self.bits >> 9) & 1) != 0)
182 }
183 #[doc = "Bit 16"]
184 #[inline(always)]
185 pub fn ahb_idle_0(&self) -> AHB_IDLE_0_R {
186 AHB_IDLE_0_R::new(((self.bits >> 16) & 1) != 0)
187 }
188 #[doc = "Bit 17"]
189 #[inline(always)]
190 pub fn ahb_idle_1(&self) -> AHB_IDLE_1_R {
191 AHB_IDLE_1_R::new(((self.bits >> 17) & 1) != 0)
192 }
193 #[doc = "Bit 19"]
194 #[inline(always)]
195 pub fn st_dvp_idle(&self) -> ST_DVP_IDLE_R {
196 ST_DVP_IDLE_R::new(((self.bits >> 19) & 1) != 0)
197 }
198 #[doc = "Bits 20:23"]
199 #[inline(always)]
200 pub fn frame_valid_cnt_0(&self) -> FRAME_VALID_CNT_0_R {
201 FRAME_VALID_CNT_0_R::new(((self.bits >> 20) & 0x0f) as u8)
202 }
203 #[doc = "Bits 24:27"]
204 #[inline(always)]
205 pub fn frame_valid_cnt_1(&self) -> FRAME_VALID_CNT_1_R {
206 FRAME_VALID_CNT_1_R::new(((self.bits >> 24) & 0x0f) as u8)
207 }
208 #[doc = "Bit 28"]
209 #[inline(always)]
210 pub fn st_bus_idle(&self) -> ST_BUS_IDLE_R {
211 ST_BUS_IDLE_R::new(((self.bits >> 28) & 1) != 0)
212 }
213 #[doc = "Bit 29"]
214 #[inline(always)]
215 pub fn st_bus_func(&self) -> ST_BUS_FUNC_R {
216 ST_BUS_FUNC_R::new(((self.bits >> 29) & 1) != 0)
217 }
218 #[doc = "Bit 30"]
219 #[inline(always)]
220 pub fn st_bus_wait(&self) -> ST_BUS_WAIT_R {
221 ST_BUS_WAIT_R::new(((self.bits >> 30) & 1) != 0)
222 }
223 #[doc = "Bit 31"]
224 #[inline(always)]
225 pub fn st_bus_flsh(&self) -> ST_BUS_FLSH_R {
226 ST_BUS_FLSH_R::new(((self.bits >> 31) & 1) != 0)
227 }
228}
229impl W {
230 #[doc = "Bit 0"]
231 #[inline(always)]
232 #[must_use]
233 pub fn sts_normal_int_0(&mut self) -> STS_NORMAL_INT_0_W<0> {
234 STS_NORMAL_INT_0_W::new(self)
235 }
236 #[doc = "Bit 1"]
237 #[inline(always)]
238 #[must_use]
239 pub fn sts_normal_int_1(&mut self) -> STS_NORMAL_INT_1_W<1> {
240 STS_NORMAL_INT_1_W::new(self)
241 }
242 #[doc = "Bit 2"]
243 #[inline(always)]
244 #[must_use]
245 pub fn sts_mem_int_0(&mut self) -> STS_MEM_INT_0_W<2> {
246 STS_MEM_INT_0_W::new(self)
247 }
248 #[doc = "Bit 3"]
249 #[inline(always)]
250 #[must_use]
251 pub fn sts_mem_int_1(&mut self) -> STS_MEM_INT_1_W<3> {
252 STS_MEM_INT_1_W::new(self)
253 }
254 #[doc = "Bit 4"]
255 #[inline(always)]
256 #[must_use]
257 pub fn sts_frame_int_0(&mut self) -> STS_FRAME_INT_0_W<4> {
258 STS_FRAME_INT_0_W::new(self)
259 }
260 #[doc = "Bit 5"]
261 #[inline(always)]
262 #[must_use]
263 pub fn sts_frame_int_1(&mut self) -> STS_FRAME_INT_1_W<5> {
264 STS_FRAME_INT_1_W::new(self)
265 }
266 #[doc = "Bit 6"]
267 #[inline(always)]
268 #[must_use]
269 pub fn sts_fifo_int_0(&mut self) -> STS_FIFO_INT_0_W<6> {
270 STS_FIFO_INT_0_W::new(self)
271 }
272 #[doc = "Bit 7"]
273 #[inline(always)]
274 #[must_use]
275 pub fn sts_fifo_int_1(&mut self) -> STS_FIFO_INT_1_W<7> {
276 STS_FIFO_INT_1_W::new(self)
277 }
278 #[doc = "Bit 8"]
279 #[inline(always)]
280 #[must_use]
281 pub fn sts_hcnt_int(&mut self) -> STS_HCNT_INT_W<8> {
282 STS_HCNT_INT_W::new(self)
283 }
284 #[doc = "Bit 9"]
285 #[inline(always)]
286 #[must_use]
287 pub fn sts_vcnt_int(&mut self) -> STS_VCNT_INT_W<9> {
288 STS_VCNT_INT_W::new(self)
289 }
290 #[doc = "Bit 16"]
291 #[inline(always)]
292 #[must_use]
293 pub fn ahb_idle_0(&mut self) -> AHB_IDLE_0_W<16> {
294 AHB_IDLE_0_W::new(self)
295 }
296 #[doc = "Bit 17"]
297 #[inline(always)]
298 #[must_use]
299 pub fn ahb_idle_1(&mut self) -> AHB_IDLE_1_W<17> {
300 AHB_IDLE_1_W::new(self)
301 }
302 #[doc = "Bit 19"]
303 #[inline(always)]
304 #[must_use]
305 pub fn st_dvp_idle(&mut self) -> ST_DVP_IDLE_W<19> {
306 ST_DVP_IDLE_W::new(self)
307 }
308 #[doc = "Bits 20:23"]
309 #[inline(always)]
310 #[must_use]
311 pub fn frame_valid_cnt_0(&mut self) -> FRAME_VALID_CNT_0_W<20> {
312 FRAME_VALID_CNT_0_W::new(self)
313 }
314 #[doc = "Bits 24:27"]
315 #[inline(always)]
316 #[must_use]
317 pub fn frame_valid_cnt_1(&mut self) -> FRAME_VALID_CNT_1_W<24> {
318 FRAME_VALID_CNT_1_W::new(self)
319 }
320 #[doc = "Bit 28"]
321 #[inline(always)]
322 #[must_use]
323 pub fn st_bus_idle(&mut self) -> ST_BUS_IDLE_W<28> {
324 ST_BUS_IDLE_W::new(self)
325 }
326 #[doc = "Bit 29"]
327 #[inline(always)]
328 #[must_use]
329 pub fn st_bus_func(&mut self) -> ST_BUS_FUNC_W<29> {
330 ST_BUS_FUNC_W::new(self)
331 }
332 #[doc = "Bit 30"]
333 #[inline(always)]
334 #[must_use]
335 pub fn st_bus_wait(&mut self) -> ST_BUS_WAIT_W<30> {
336 ST_BUS_WAIT_W::new(self)
337 }
338 #[doc = "Bit 31"]
339 #[inline(always)]
340 #[must_use]
341 pub fn st_bus_flsh(&mut self) -> ST_BUS_FLSH_W<31> {
342 ST_BUS_FLSH_W::new(self)
343 }
344 #[doc = "Writes raw bits to the register."]
345 #[inline(always)]
346 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
347 self.0.bits(bits);
348 self
349 }
350}
351#[doc = "dvp_status_and_error.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvp_status_and_error](index.html) module"]
352pub struct DVP_STATUS_AND_ERROR_SPEC;
353impl crate::RegisterSpec for DVP_STATUS_AND_ERROR_SPEC {
354 type Ux = u32;
355}
356#[doc = "`read()` method returns [dvp_status_and_error::R](R) reader structure"]
357impl crate::Readable for DVP_STATUS_AND_ERROR_SPEC {
358 type Reader = R;
359}
360#[doc = "`write(|w| ..)` method takes [dvp_status_and_error::W](W) writer structure"]
361impl crate::Writable for DVP_STATUS_AND_ERROR_SPEC {
362 type Writer = W;
363 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
364 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
365}
366#[doc = "`reset()` method sets dvp_status_and_error to value 0"]
367impl crate::Resettable for DVP_STATUS_AND_ERROR_SPEC {
368 const RESET_VALUE: Self::Ux = 0;
369}