bl702_pac/cam/
dvp2axi_configue.rs1#[doc = "Register `dvp2axi_configue` reader"]
2pub struct R(crate::R<DVP2AXI_CONFIGUE_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DVP2AXI_CONFIGUE_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DVP2AXI_CONFIGUE_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DVP2AXI_CONFIGUE_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `dvp2axi_configue` writer"]
17pub struct W(crate::W<DVP2AXI_CONFIGUE_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DVP2AXI_CONFIGUE_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DVP2AXI_CONFIGUE_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DVP2AXI_CONFIGUE_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `reg_dvp_enable` reader - "]
38pub type REG_DVP_ENABLE_R = crate::BitReader<bool>;
39#[doc = "Field `reg_dvp_enable` writer - "]
40pub type REG_DVP_ENABLE_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
42#[doc = "Field `reg_sw_mode` reader - "]
43pub type REG_SW_MODE_R = crate::BitReader<bool>;
44#[doc = "Field `reg_sw_mode` writer - "]
45pub type REG_SW_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
46#[doc = "Field `reg_fram_vld_pol` reader - "]
47pub type REG_FRAM_VLD_POL_R = crate::BitReader<bool>;
48#[doc = "Field `reg_fram_vld_pol` writer - "]
49pub type REG_FRAM_VLD_POL_W<'a, const O: u8> =
50 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
51#[doc = "Field `reg_line_vld_pol` reader - "]
52pub type REG_LINE_VLD_POL_R = crate::BitReader<bool>;
53#[doc = "Field `reg_line_vld_pol` writer - "]
54pub type REG_LINE_VLD_POL_W<'a, const O: u8> =
55 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
56#[doc = "Field `reg_hburst` reader - "]
57pub type REG_HBURST_R = crate::FieldReader<u8, u8>;
58#[doc = "Field `reg_hburst` writer - "]
59pub type REG_HBURST_W<'a, const O: u8> =
60 crate::FieldWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, u8, u8, 2, O>;
61#[doc = "Field `reg_dvp_mode` reader - "]
62pub type REG_DVP_MODE_R = crate::FieldReader<u8, u8>;
63#[doc = "Field `reg_dvp_mode` writer - "]
64pub type REG_DVP_MODE_W<'a, const O: u8> =
65 crate::FieldWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, u8, u8, 3, O>;
66#[doc = "Field `reg_hw_mode_fwrap` reader - "]
67pub type REG_HW_MODE_FWRAP_R = crate::BitReader<bool>;
68#[doc = "Field `reg_hw_mode_fwrap` writer - "]
69pub type REG_HW_MODE_FWRAP_W<'a, const O: u8> =
70 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
71#[doc = "Field `reg_drop_en` reader - "]
72pub type REG_DROP_EN_R = crate::BitReader<bool>;
73#[doc = "Field `reg_drop_en` writer - "]
74pub type REG_DROP_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
75#[doc = "Field `reg_drop_even` reader - "]
76pub type REG_DROP_EVEN_R = crate::BitReader<bool>;
77#[doc = "Field `reg_drop_even` writer - "]
78pub type REG_DROP_EVEN_W<'a, const O: u8> =
79 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
80#[doc = "Field `reg_subsample_en` reader - "]
81pub type REG_SUBSAMPLE_EN_R = crate::BitReader<bool>;
82#[doc = "Field `reg_subsample_en` writer - "]
83pub type REG_SUBSAMPLE_EN_W<'a, const O: u8> =
84 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
85#[doc = "Field `reg_subsample_even` reader - "]
86pub type REG_SUBSAMPLE_EVEN_R = crate::BitReader<bool>;
87#[doc = "Field `reg_subsample_even` writer - "]
88pub type REG_SUBSAMPLE_EVEN_W<'a, const O: u8> =
89 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
90#[doc = "Field `reg_interlv_mode` reader - "]
91pub type REG_INTERLV_MODE_R = crate::BitReader<bool>;
92#[doc = "Field `reg_interlv_mode` writer - "]
93pub type REG_INTERLV_MODE_W<'a, const O: u8> =
94 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
95#[doc = "Field `reg_dvp_pix_clk_cg` reader - "]
96pub type REG_DVP_PIX_CLK_CG_R = crate::BitReader<bool>;
97#[doc = "Field `reg_dvp_pix_clk_cg` writer - "]
98pub type REG_DVP_PIX_CLK_CG_W<'a, const O: u8> =
99 crate::BitWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, bool, O>;
100#[doc = "Field `reg_dvp_wait_cycle` reader - "]
101pub type REG_DVP_WAIT_CYCLE_R = crate::FieldReader<u8, u8>;
102#[doc = "Field `reg_dvp_wait_cycle` writer - "]
103pub type REG_DVP_WAIT_CYCLE_W<'a, const O: u8> =
104 crate::FieldWriter<'a, u32, DVP2AXI_CONFIGUE_SPEC, u8, u8, 8, O>;
105impl R {
106 #[doc = "Bit 0"]
107 #[inline(always)]
108 pub fn reg_dvp_enable(&self) -> REG_DVP_ENABLE_R {
109 REG_DVP_ENABLE_R::new((self.bits & 1) != 0)
110 }
111 #[doc = "Bit 1"]
112 #[inline(always)]
113 pub fn reg_sw_mode(&self) -> REG_SW_MODE_R {
114 REG_SW_MODE_R::new(((self.bits >> 1) & 1) != 0)
115 }
116 #[doc = "Bit 2"]
117 #[inline(always)]
118 pub fn reg_fram_vld_pol(&self) -> REG_FRAM_VLD_POL_R {
119 REG_FRAM_VLD_POL_R::new(((self.bits >> 2) & 1) != 0)
120 }
121 #[doc = "Bit 3"]
122 #[inline(always)]
123 pub fn reg_line_vld_pol(&self) -> REG_LINE_VLD_POL_R {
124 REG_LINE_VLD_POL_R::new(((self.bits >> 3) & 1) != 0)
125 }
126 #[doc = "Bits 4:5"]
127 #[inline(always)]
128 pub fn reg_hburst(&self) -> REG_HBURST_R {
129 REG_HBURST_R::new(((self.bits >> 4) & 3) as u8)
130 }
131 #[doc = "Bits 8:10"]
132 #[inline(always)]
133 pub fn reg_dvp_mode(&self) -> REG_DVP_MODE_R {
134 REG_DVP_MODE_R::new(((self.bits >> 8) & 7) as u8)
135 }
136 #[doc = "Bit 11"]
137 #[inline(always)]
138 pub fn reg_hw_mode_fwrap(&self) -> REG_HW_MODE_FWRAP_R {
139 REG_HW_MODE_FWRAP_R::new(((self.bits >> 11) & 1) != 0)
140 }
141 #[doc = "Bit 12"]
142 #[inline(always)]
143 pub fn reg_drop_en(&self) -> REG_DROP_EN_R {
144 REG_DROP_EN_R::new(((self.bits >> 12) & 1) != 0)
145 }
146 #[doc = "Bit 13"]
147 #[inline(always)]
148 pub fn reg_drop_even(&self) -> REG_DROP_EVEN_R {
149 REG_DROP_EVEN_R::new(((self.bits >> 13) & 1) != 0)
150 }
151 #[doc = "Bit 14"]
152 #[inline(always)]
153 pub fn reg_subsample_en(&self) -> REG_SUBSAMPLE_EN_R {
154 REG_SUBSAMPLE_EN_R::new(((self.bits >> 14) & 1) != 0)
155 }
156 #[doc = "Bit 15"]
157 #[inline(always)]
158 pub fn reg_subsample_even(&self) -> REG_SUBSAMPLE_EVEN_R {
159 REG_SUBSAMPLE_EVEN_R::new(((self.bits >> 15) & 1) != 0)
160 }
161 #[doc = "Bit 16"]
162 #[inline(always)]
163 pub fn reg_interlv_mode(&self) -> REG_INTERLV_MODE_R {
164 REG_INTERLV_MODE_R::new(((self.bits >> 16) & 1) != 0)
165 }
166 #[doc = "Bit 20"]
167 #[inline(always)]
168 pub fn reg_dvp_pix_clk_cg(&self) -> REG_DVP_PIX_CLK_CG_R {
169 REG_DVP_PIX_CLK_CG_R::new(((self.bits >> 20) & 1) != 0)
170 }
171 #[doc = "Bits 24:31"]
172 #[inline(always)]
173 pub fn reg_dvp_wait_cycle(&self) -> REG_DVP_WAIT_CYCLE_R {
174 REG_DVP_WAIT_CYCLE_R::new(((self.bits >> 24) & 0xff) as u8)
175 }
176}
177impl W {
178 #[doc = "Bit 0"]
179 #[inline(always)]
180 #[must_use]
181 pub fn reg_dvp_enable(&mut self) -> REG_DVP_ENABLE_W<0> {
182 REG_DVP_ENABLE_W::new(self)
183 }
184 #[doc = "Bit 1"]
185 #[inline(always)]
186 #[must_use]
187 pub fn reg_sw_mode(&mut self) -> REG_SW_MODE_W<1> {
188 REG_SW_MODE_W::new(self)
189 }
190 #[doc = "Bit 2"]
191 #[inline(always)]
192 #[must_use]
193 pub fn reg_fram_vld_pol(&mut self) -> REG_FRAM_VLD_POL_W<2> {
194 REG_FRAM_VLD_POL_W::new(self)
195 }
196 #[doc = "Bit 3"]
197 #[inline(always)]
198 #[must_use]
199 pub fn reg_line_vld_pol(&mut self) -> REG_LINE_VLD_POL_W<3> {
200 REG_LINE_VLD_POL_W::new(self)
201 }
202 #[doc = "Bits 4:5"]
203 #[inline(always)]
204 #[must_use]
205 pub fn reg_hburst(&mut self) -> REG_HBURST_W<4> {
206 REG_HBURST_W::new(self)
207 }
208 #[doc = "Bits 8:10"]
209 #[inline(always)]
210 #[must_use]
211 pub fn reg_dvp_mode(&mut self) -> REG_DVP_MODE_W<8> {
212 REG_DVP_MODE_W::new(self)
213 }
214 #[doc = "Bit 11"]
215 #[inline(always)]
216 #[must_use]
217 pub fn reg_hw_mode_fwrap(&mut self) -> REG_HW_MODE_FWRAP_W<11> {
218 REG_HW_MODE_FWRAP_W::new(self)
219 }
220 #[doc = "Bit 12"]
221 #[inline(always)]
222 #[must_use]
223 pub fn reg_drop_en(&mut self) -> REG_DROP_EN_W<12> {
224 REG_DROP_EN_W::new(self)
225 }
226 #[doc = "Bit 13"]
227 #[inline(always)]
228 #[must_use]
229 pub fn reg_drop_even(&mut self) -> REG_DROP_EVEN_W<13> {
230 REG_DROP_EVEN_W::new(self)
231 }
232 #[doc = "Bit 14"]
233 #[inline(always)]
234 #[must_use]
235 pub fn reg_subsample_en(&mut self) -> REG_SUBSAMPLE_EN_W<14> {
236 REG_SUBSAMPLE_EN_W::new(self)
237 }
238 #[doc = "Bit 15"]
239 #[inline(always)]
240 #[must_use]
241 pub fn reg_subsample_even(&mut self) -> REG_SUBSAMPLE_EVEN_W<15> {
242 REG_SUBSAMPLE_EVEN_W::new(self)
243 }
244 #[doc = "Bit 16"]
245 #[inline(always)]
246 #[must_use]
247 pub fn reg_interlv_mode(&mut self) -> REG_INTERLV_MODE_W<16> {
248 REG_INTERLV_MODE_W::new(self)
249 }
250 #[doc = "Bit 20"]
251 #[inline(always)]
252 #[must_use]
253 pub fn reg_dvp_pix_clk_cg(&mut self) -> REG_DVP_PIX_CLK_CG_W<20> {
254 REG_DVP_PIX_CLK_CG_W::new(self)
255 }
256 #[doc = "Bits 24:31"]
257 #[inline(always)]
258 #[must_use]
259 pub fn reg_dvp_wait_cycle(&mut self) -> REG_DVP_WAIT_CYCLE_W<24> {
260 REG_DVP_WAIT_CYCLE_W::new(self)
261 }
262 #[doc = "Writes raw bits to the register."]
263 #[inline(always)]
264 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
265 self.0.bits(bits);
266 self
267 }
268}
269#[doc = "dvp2axi_configue.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dvp2axi_configue](index.html) module"]
270pub struct DVP2AXI_CONFIGUE_SPEC;
271impl crate::RegisterSpec for DVP2AXI_CONFIGUE_SPEC {
272 type Ux = u32;
273}
274#[doc = "`read()` method returns [dvp2axi_configue::R](R) reader structure"]
275impl crate::Readable for DVP2AXI_CONFIGUE_SPEC {
276 type Reader = R;
277}
278#[doc = "`write(|w| ..)` method takes [dvp2axi_configue::W](W) writer structure"]
279impl crate::Writable for DVP2AXI_CONFIGUE_SPEC {
280 type Writer = W;
281 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
282 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
283}
284#[doc = "`reset()` method sets dvp2axi_configue to value 0"]
285impl crate::Resettable for DVP2AXI_CONFIGUE_SPEC {
286 const RESET_VALUE: Self::Ux = 0;
287}