bl702_pac/aon/
dcdc18_top_1.rs1#[doc = "Register `dcdc18_top_1` reader"]
2pub struct R(crate::R<DCDC18_TOP_1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DCDC18_TOP_1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DCDC18_TOP_1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DCDC18_TOP_1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `dcdc18_top_1` writer"]
17pub struct W(crate::W<DCDC18_TOP_1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DCDC18_TOP_1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DCDC18_TOP_1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DCDC18_TOP_1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `dcdc18_force_cs_zvs_aon` reader - "]
38pub type DCDC18_FORCE_CS_ZVS_AON_R = crate::BitReader<bool>;
39#[doc = "Field `dcdc18_force_cs_zvs_aon` writer - "]
40pub type DCDC18_FORCE_CS_ZVS_AON_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, DCDC18_TOP_1_SPEC, bool, O>;
42#[doc = "Field `dcdc18_cs_delay_aon` reader - "]
43pub type DCDC18_CS_DELAY_AON_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `dcdc18_cs_delay_aon` writer - "]
45pub type DCDC18_CS_DELAY_AON_W<'a, const O: u8> =
46 crate::FieldWriter<'a, u32, DCDC18_TOP_1_SPEC, u8, u8, 3, O>;
47#[doc = "Field `dcdc18_zvs_td_opt_aon` reader - "]
48pub type DCDC18_ZVS_TD_OPT_AON_R = crate::FieldReader<u8, u8>;
49#[doc = "Field `dcdc18_zvs_td_opt_aon` writer - "]
50pub type DCDC18_ZVS_TD_OPT_AON_W<'a, const O: u8> =
51 crate::FieldWriter<'a, u32, DCDC18_TOP_1_SPEC, u8, u8, 3, O>;
52#[doc = "Field `dcdc18_nonoverlap_td_aon` reader - "]
53pub type DCDC18_NONOVERLAP_TD_AON_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `dcdc18_nonoverlap_td_aon` writer - "]
55pub type DCDC18_NONOVERLAP_TD_AON_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, DCDC18_TOP_1_SPEC, u8, u8, 5, O>;
57#[doc = "Field `dcdc18_rc_sel_aon` reader - "]
58pub type DCDC18_RC_SEL_AON_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `dcdc18_rc_sel_aon` writer - "]
60pub type DCDC18_RC_SEL_AON_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, DCDC18_TOP_1_SPEC, u8, u8, 4, O>;
62#[doc = "Field `dcdc18_chf_sel_aon` reader - "]
63pub type DCDC18_CHF_SEL_AON_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `dcdc18_chf_sel_aon` writer - "]
65pub type DCDC18_CHF_SEL_AON_W<'a, const O: u8> =
66 crate::FieldWriter<'a, u32, DCDC18_TOP_1_SPEC, u8, u8, 4, O>;
67#[doc = "Field `dcdc18_cfb_sel_aon` reader - "]
68pub type DCDC18_CFB_SEL_AON_R = crate::FieldReader<u8, u8>;
69#[doc = "Field `dcdc18_cfb_sel_aon` writer - "]
70pub type DCDC18_CFB_SEL_AON_W<'a, const O: u8> =
71 crate::FieldWriter<'a, u32, DCDC18_TOP_1_SPEC, u8, u8, 4, O>;
72#[doc = "Field `dcdc18_en_antiring_aon` reader - "]
73pub type DCDC18_EN_ANTIRING_AON_R = crate::BitReader<bool>;
74#[doc = "Field `dcdc18_en_antiring_aon` writer - "]
75pub type DCDC18_EN_ANTIRING_AON_W<'a, const O: u8> =
76 crate::BitWriter<'a, u32, DCDC18_TOP_1_SPEC, bool, O>;
77#[doc = "Field `dcdc18_pulldown_aon` reader - "]
78pub type DCDC18_PULLDOWN_AON_R = crate::BitReader<bool>;
79#[doc = "Field `dcdc18_pulldown_aon` writer - "]
80pub type DCDC18_PULLDOWN_AON_W<'a, const O: u8> =
81 crate::BitWriter<'a, u32, DCDC18_TOP_1_SPEC, bool, O>;
82impl R {
83 #[doc = "Bit 0"]
84 #[inline(always)]
85 pub fn dcdc18_force_cs_zvs_aon(&self) -> DCDC18_FORCE_CS_ZVS_AON_R {
86 DCDC18_FORCE_CS_ZVS_AON_R::new((self.bits & 1) != 0)
87 }
88 #[doc = "Bits 1:3"]
89 #[inline(always)]
90 pub fn dcdc18_cs_delay_aon(&self) -> DCDC18_CS_DELAY_AON_R {
91 DCDC18_CS_DELAY_AON_R::new(((self.bits >> 1) & 7) as u8)
92 }
93 #[doc = "Bits 4:6"]
94 #[inline(always)]
95 pub fn dcdc18_zvs_td_opt_aon(&self) -> DCDC18_ZVS_TD_OPT_AON_R {
96 DCDC18_ZVS_TD_OPT_AON_R::new(((self.bits >> 4) & 7) as u8)
97 }
98 #[doc = "Bits 8:12"]
99 #[inline(always)]
100 pub fn dcdc18_nonoverlap_td_aon(&self) -> DCDC18_NONOVERLAP_TD_AON_R {
101 DCDC18_NONOVERLAP_TD_AON_R::new(((self.bits >> 8) & 0x1f) as u8)
102 }
103 #[doc = "Bits 16:19"]
104 #[inline(always)]
105 pub fn dcdc18_rc_sel_aon(&self) -> DCDC18_RC_SEL_AON_R {
106 DCDC18_RC_SEL_AON_R::new(((self.bits >> 16) & 0x0f) as u8)
107 }
108 #[doc = "Bits 20:23"]
109 #[inline(always)]
110 pub fn dcdc18_chf_sel_aon(&self) -> DCDC18_CHF_SEL_AON_R {
111 DCDC18_CHF_SEL_AON_R::new(((self.bits >> 20) & 0x0f) as u8)
112 }
113 #[doc = "Bits 24:27"]
114 #[inline(always)]
115 pub fn dcdc18_cfb_sel_aon(&self) -> DCDC18_CFB_SEL_AON_R {
116 DCDC18_CFB_SEL_AON_R::new(((self.bits >> 24) & 0x0f) as u8)
117 }
118 #[doc = "Bit 28"]
119 #[inline(always)]
120 pub fn dcdc18_en_antiring_aon(&self) -> DCDC18_EN_ANTIRING_AON_R {
121 DCDC18_EN_ANTIRING_AON_R::new(((self.bits >> 28) & 1) != 0)
122 }
123 #[doc = "Bit 29"]
124 #[inline(always)]
125 pub fn dcdc18_pulldown_aon(&self) -> DCDC18_PULLDOWN_AON_R {
126 DCDC18_PULLDOWN_AON_R::new(((self.bits >> 29) & 1) != 0)
127 }
128}
129impl W {
130 #[doc = "Bit 0"]
131 #[inline(always)]
132 #[must_use]
133 pub fn dcdc18_force_cs_zvs_aon(&mut self) -> DCDC18_FORCE_CS_ZVS_AON_W<0> {
134 DCDC18_FORCE_CS_ZVS_AON_W::new(self)
135 }
136 #[doc = "Bits 1:3"]
137 #[inline(always)]
138 #[must_use]
139 pub fn dcdc18_cs_delay_aon(&mut self) -> DCDC18_CS_DELAY_AON_W<1> {
140 DCDC18_CS_DELAY_AON_W::new(self)
141 }
142 #[doc = "Bits 4:6"]
143 #[inline(always)]
144 #[must_use]
145 pub fn dcdc18_zvs_td_opt_aon(&mut self) -> DCDC18_ZVS_TD_OPT_AON_W<4> {
146 DCDC18_ZVS_TD_OPT_AON_W::new(self)
147 }
148 #[doc = "Bits 8:12"]
149 #[inline(always)]
150 #[must_use]
151 pub fn dcdc18_nonoverlap_td_aon(&mut self) -> DCDC18_NONOVERLAP_TD_AON_W<8> {
152 DCDC18_NONOVERLAP_TD_AON_W::new(self)
153 }
154 #[doc = "Bits 16:19"]
155 #[inline(always)]
156 #[must_use]
157 pub fn dcdc18_rc_sel_aon(&mut self) -> DCDC18_RC_SEL_AON_W<16> {
158 DCDC18_RC_SEL_AON_W::new(self)
159 }
160 #[doc = "Bits 20:23"]
161 #[inline(always)]
162 #[must_use]
163 pub fn dcdc18_chf_sel_aon(&mut self) -> DCDC18_CHF_SEL_AON_W<20> {
164 DCDC18_CHF_SEL_AON_W::new(self)
165 }
166 #[doc = "Bits 24:27"]
167 #[inline(always)]
168 #[must_use]
169 pub fn dcdc18_cfb_sel_aon(&mut self) -> DCDC18_CFB_SEL_AON_W<24> {
170 DCDC18_CFB_SEL_AON_W::new(self)
171 }
172 #[doc = "Bit 28"]
173 #[inline(always)]
174 #[must_use]
175 pub fn dcdc18_en_antiring_aon(&mut self) -> DCDC18_EN_ANTIRING_AON_W<28> {
176 DCDC18_EN_ANTIRING_AON_W::new(self)
177 }
178 #[doc = "Bit 29"]
179 #[inline(always)]
180 #[must_use]
181 pub fn dcdc18_pulldown_aon(&mut self) -> DCDC18_PULLDOWN_AON_W<29> {
182 DCDC18_PULLDOWN_AON_W::new(self)
183 }
184 #[doc = "Writes raw bits to the register."]
185 #[inline(always)]
186 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
187 self.0.bits(bits);
188 self
189 }
190}
191#[doc = "dcdc18_top_1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcdc18_top_1](index.html) module"]
192pub struct DCDC18_TOP_1_SPEC;
193impl crate::RegisterSpec for DCDC18_TOP_1_SPEC {
194 type Ux = u32;
195}
196#[doc = "`read()` method returns [dcdc18_top_1::R](R) reader structure"]
197impl crate::Readable for DCDC18_TOP_1_SPEC {
198 type Reader = R;
199}
200#[doc = "`write(|w| ..)` method takes [dcdc18_top_1::W](W) writer structure"]
201impl crate::Writable for DCDC18_TOP_1_SPEC {
202 type Writer = W;
203 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
204 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205}
206#[doc = "`reset()` method sets dcdc18_top_1 to value 0"]
207impl crate::Resettable for DCDC18_TOP_1_SPEC {
208 const RESET_VALUE: Self::Ux = 0;
209}