bl702_pac/aon/
dcdc18_top_0.rs1#[doc = "Register `dcdc18_top_0` reader"]
2pub struct R(crate::R<DCDC18_TOP_0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DCDC18_TOP_0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DCDC18_TOP_0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DCDC18_TOP_0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `dcdc18_top_0` writer"]
17pub struct W(crate::W<DCDC18_TOP_0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DCDC18_TOP_0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DCDC18_TOP_0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DCDC18_TOP_0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `dcdc18_vout_sel_aon` reader - "]
38pub type DCDC18_VOUT_SEL_AON_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `dcdc18_vout_sel_aon` writer - "]
40pub type DCDC18_VOUT_SEL_AON_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 5, O>;
42#[doc = "Field `dcdc18_vpfm_aon` reader - "]
43pub type DCDC18_VPFM_AON_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `dcdc18_vpfm_aon` writer - "]
45pub type DCDC18_VPFM_AON_W<'a, const O: u8> =
46 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 4, O>;
47#[doc = "Field `dcdc18_osc_2m_mode_aon` reader - "]
48pub type DCDC18_OSC_2M_MODE_AON_R = crate::BitReader<bool>;
49#[doc = "Field `dcdc18_osc_2m_mode_aon` writer - "]
50pub type DCDC18_OSC_2M_MODE_AON_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
52#[doc = "Field `dcdc18_osc_freq_trim_aon` reader - "]
53pub type DCDC18_OSC_FREQ_TRIM_AON_R = crate::FieldReader<u8, u8>;
54#[doc = "Field `dcdc18_osc_freq_trim_aon` writer - "]
55pub type DCDC18_OSC_FREQ_TRIM_AON_W<'a, const O: u8> =
56 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 4, O>;
57#[doc = "Field `dcdc18_slope_curr_sel_aon` reader - "]
58pub type DCDC18_SLOPE_CURR_SEL_AON_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `dcdc18_slope_curr_sel_aon` writer - "]
60pub type DCDC18_SLOPE_CURR_SEL_AON_W<'a, const O: u8> =
61 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 5, O>;
62#[doc = "Field `dcdc18_stop_osc_aon` reader - "]
63pub type DCDC18_STOP_OSC_AON_R = crate::BitReader<bool>;
64#[doc = "Field `dcdc18_stop_osc_aon` writer - "]
65pub type DCDC18_STOP_OSC_AON_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
67#[doc = "Field `dcdc18_slow_osc_aon` reader - "]
68pub type DCDC18_SLOW_OSC_AON_R = crate::BitReader<bool>;
69#[doc = "Field `dcdc18_slow_osc_aon` writer - "]
70pub type DCDC18_SLOW_OSC_AON_W<'a, const O: u8> =
71 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
72#[doc = "Field `dcdc18_osc_inhibit_t2_aon` reader - "]
73pub type DCDC18_OSC_INHIBIT_T2_AON_R = crate::BitReader<bool>;
74#[doc = "Field `dcdc18_osc_inhibit_t2_aon` writer - "]
75pub type DCDC18_OSC_INHIBIT_T2_AON_W<'a, const O: u8> =
76 crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
77#[doc = "Field `dcdc18_sstart_time_aon` reader - "]
78pub type DCDC18_SSTART_TIME_AON_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `dcdc18_sstart_time_aon` writer - "]
80pub type DCDC18_SSTART_TIME_AON_W<'a, const O: u8> =
81 crate::FieldWriter<'a, u32, DCDC18_TOP_0_SPEC, u8, u8, 2, O>;
82#[doc = "Field `dcdc18_rdy_aon` reader - "]
83pub type DCDC18_RDY_AON_R = crate::BitReader<bool>;
84#[doc = "Field `dcdc18_rdy_aon` writer - "]
85pub type DCDC18_RDY_AON_W<'a, const O: u8> = crate::BitWriter<'a, u32, DCDC18_TOP_0_SPEC, bool, O>;
86impl R {
87 #[doc = "Bits 1:5"]
88 #[inline(always)]
89 pub fn dcdc18_vout_sel_aon(&self) -> DCDC18_VOUT_SEL_AON_R {
90 DCDC18_VOUT_SEL_AON_R::new(((self.bits >> 1) & 0x1f) as u8)
91 }
92 #[doc = "Bits 8:11"]
93 #[inline(always)]
94 pub fn dcdc18_vpfm_aon(&self) -> DCDC18_VPFM_AON_R {
95 DCDC18_VPFM_AON_R::new(((self.bits >> 8) & 0x0f) as u8)
96 }
97 #[doc = "Bit 12"]
98 #[inline(always)]
99 pub fn dcdc18_osc_2m_mode_aon(&self) -> DCDC18_OSC_2M_MODE_AON_R {
100 DCDC18_OSC_2M_MODE_AON_R::new(((self.bits >> 12) & 1) != 0)
101 }
102 #[doc = "Bits 16:19"]
103 #[inline(always)]
104 pub fn dcdc18_osc_freq_trim_aon(&self) -> DCDC18_OSC_FREQ_TRIM_AON_R {
105 DCDC18_OSC_FREQ_TRIM_AON_R::new(((self.bits >> 16) & 0x0f) as u8)
106 }
107 #[doc = "Bits 20:24"]
108 #[inline(always)]
109 pub fn dcdc18_slope_curr_sel_aon(&self) -> DCDC18_SLOPE_CURR_SEL_AON_R {
110 DCDC18_SLOPE_CURR_SEL_AON_R::new(((self.bits >> 20) & 0x1f) as u8)
111 }
112 #[doc = "Bit 25"]
113 #[inline(always)]
114 pub fn dcdc18_stop_osc_aon(&self) -> DCDC18_STOP_OSC_AON_R {
115 DCDC18_STOP_OSC_AON_R::new(((self.bits >> 25) & 1) != 0)
116 }
117 #[doc = "Bit 26"]
118 #[inline(always)]
119 pub fn dcdc18_slow_osc_aon(&self) -> DCDC18_SLOW_OSC_AON_R {
120 DCDC18_SLOW_OSC_AON_R::new(((self.bits >> 26) & 1) != 0)
121 }
122 #[doc = "Bit 27"]
123 #[inline(always)]
124 pub fn dcdc18_osc_inhibit_t2_aon(&self) -> DCDC18_OSC_INHIBIT_T2_AON_R {
125 DCDC18_OSC_INHIBIT_T2_AON_R::new(((self.bits >> 27) & 1) != 0)
126 }
127 #[doc = "Bits 28:29"]
128 #[inline(always)]
129 pub fn dcdc18_sstart_time_aon(&self) -> DCDC18_SSTART_TIME_AON_R {
130 DCDC18_SSTART_TIME_AON_R::new(((self.bits >> 28) & 3) as u8)
131 }
132 #[doc = "Bit 31"]
133 #[inline(always)]
134 pub fn dcdc18_rdy_aon(&self) -> DCDC18_RDY_AON_R {
135 DCDC18_RDY_AON_R::new(((self.bits >> 31) & 1) != 0)
136 }
137}
138impl W {
139 #[doc = "Bits 1:5"]
140 #[inline(always)]
141 #[must_use]
142 pub fn dcdc18_vout_sel_aon(&mut self) -> DCDC18_VOUT_SEL_AON_W<1> {
143 DCDC18_VOUT_SEL_AON_W::new(self)
144 }
145 #[doc = "Bits 8:11"]
146 #[inline(always)]
147 #[must_use]
148 pub fn dcdc18_vpfm_aon(&mut self) -> DCDC18_VPFM_AON_W<8> {
149 DCDC18_VPFM_AON_W::new(self)
150 }
151 #[doc = "Bit 12"]
152 #[inline(always)]
153 #[must_use]
154 pub fn dcdc18_osc_2m_mode_aon(&mut self) -> DCDC18_OSC_2M_MODE_AON_W<12> {
155 DCDC18_OSC_2M_MODE_AON_W::new(self)
156 }
157 #[doc = "Bits 16:19"]
158 #[inline(always)]
159 #[must_use]
160 pub fn dcdc18_osc_freq_trim_aon(&mut self) -> DCDC18_OSC_FREQ_TRIM_AON_W<16> {
161 DCDC18_OSC_FREQ_TRIM_AON_W::new(self)
162 }
163 #[doc = "Bits 20:24"]
164 #[inline(always)]
165 #[must_use]
166 pub fn dcdc18_slope_curr_sel_aon(&mut self) -> DCDC18_SLOPE_CURR_SEL_AON_W<20> {
167 DCDC18_SLOPE_CURR_SEL_AON_W::new(self)
168 }
169 #[doc = "Bit 25"]
170 #[inline(always)]
171 #[must_use]
172 pub fn dcdc18_stop_osc_aon(&mut self) -> DCDC18_STOP_OSC_AON_W<25> {
173 DCDC18_STOP_OSC_AON_W::new(self)
174 }
175 #[doc = "Bit 26"]
176 #[inline(always)]
177 #[must_use]
178 pub fn dcdc18_slow_osc_aon(&mut self) -> DCDC18_SLOW_OSC_AON_W<26> {
179 DCDC18_SLOW_OSC_AON_W::new(self)
180 }
181 #[doc = "Bit 27"]
182 #[inline(always)]
183 #[must_use]
184 pub fn dcdc18_osc_inhibit_t2_aon(&mut self) -> DCDC18_OSC_INHIBIT_T2_AON_W<27> {
185 DCDC18_OSC_INHIBIT_T2_AON_W::new(self)
186 }
187 #[doc = "Bits 28:29"]
188 #[inline(always)]
189 #[must_use]
190 pub fn dcdc18_sstart_time_aon(&mut self) -> DCDC18_SSTART_TIME_AON_W<28> {
191 DCDC18_SSTART_TIME_AON_W::new(self)
192 }
193 #[doc = "Bit 31"]
194 #[inline(always)]
195 #[must_use]
196 pub fn dcdc18_rdy_aon(&mut self) -> DCDC18_RDY_AON_W<31> {
197 DCDC18_RDY_AON_W::new(self)
198 }
199 #[doc = "Writes raw bits to the register."]
200 #[inline(always)]
201 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
202 self.0.bits(bits);
203 self
204 }
205}
206#[doc = "dcdc18_top_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcdc18_top_0](index.html) module"]
207pub struct DCDC18_TOP_0_SPEC;
208impl crate::RegisterSpec for DCDC18_TOP_0_SPEC {
209 type Ux = u32;
210}
211#[doc = "`read()` method returns [dcdc18_top_0::R](R) reader structure"]
212impl crate::Readable for DCDC18_TOP_0_SPEC {
213 type Reader = R;
214}
215#[doc = "`write(|w| ..)` method takes [dcdc18_top_0::W](W) writer structure"]
216impl crate::Writable for DCDC18_TOP_0_SPEC {
217 type Writer = W;
218 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
219 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
220}
221#[doc = "`reset()` method sets dcdc18_top_0 to value 0"]
222impl crate::Resettable for DCDC18_TOP_0_SPEC {
223 const RESET_VALUE: Self::Ux = 0;
224}