1#[doc = "Register `l1c_config` reader"]
2pub struct R(crate::R<L1C_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<L1C_CONFIG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<L1C_CONFIG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<L1C_CONFIG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `l1c_config` writer"]
17pub struct W(crate::W<L1C_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<L1C_CONFIG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<L1C_CONFIG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<L1C_CONFIG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `l1c_cacheable` reader - "]
38pub type L1C_CACHEABLE_R = crate::BitReader<bool>;
39#[doc = "Field `l1c_cacheable` writer - "]
40pub type L1C_CACHEABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
41#[doc = "Field `l1c_cnt_en` reader - "]
42pub type L1C_CNT_EN_R = crate::BitReader<bool>;
43#[doc = "Field `l1c_cnt_en` writer - "]
44pub type L1C_CNT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
45#[doc = "Field `l1c_invalid_en` reader - "]
46pub type L1C_INVALID_EN_R = crate::BitReader<bool>;
47#[doc = "Field `l1c_invalid_en` writer - "]
48pub type L1C_INVALID_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
49#[doc = "Field `l1c_invalid_done` reader - "]
50pub type L1C_INVALID_DONE_R = crate::BitReader<bool>;
51#[doc = "Field `l1c_invalid_done` writer - "]
52pub type L1C_INVALID_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
53#[doc = "Field `l1c_wt_en` reader - "]
54pub type L1C_WT_EN_R = crate::BitReader<bool>;
55#[doc = "Field `l1c_wt_en` writer - "]
56pub type L1C_WT_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
57#[doc = "Field `l1c_wb_en` reader - "]
58pub type L1C_WB_EN_R = crate::BitReader<bool>;
59#[doc = "Field `l1c_wb_en` writer - "]
60pub type L1C_WB_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
61#[doc = "Field `l1c_wa_en` reader - "]
62pub type L1C_WA_EN_R = crate::BitReader<bool>;
63#[doc = "Field `l1c_wa_en` writer - "]
64pub type L1C_WA_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
65#[doc = "Field `l1c_way_dis` reader - "]
66pub type L1C_WAY_DIS_R = crate::FieldReader<u8, u8>;
67#[doc = "Field `l1c_way_dis` writer - "]
68pub type L1C_WAY_DIS_W<'a, const O: u8> =
69 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 4, O>;
70#[doc = "Field `irom_2t_access` reader - "]
71pub type IROM_2T_ACCESS_R = crate::BitReader<bool>;
72#[doc = "Field `irom_2t_access` writer - "]
73pub type IROM_2T_ACCESS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
74#[doc = "Field `l1c_bypass` reader - "]
75pub type L1C_BYPASS_R = crate::BitReader<bool>;
76#[doc = "Field `l1c_bypass` writer - "]
77pub type L1C_BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
78#[doc = "Field `l1c_bmx_err_en` reader - "]
79pub type L1C_BMX_ERR_EN_R = crate::BitReader<bool>;
80#[doc = "Field `l1c_bmx_err_en` writer - "]
81pub type L1C_BMX_ERR_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
82#[doc = "Field `l1c_bmx_arb_mode` reader - "]
83pub type L1C_BMX_ARB_MODE_R = crate::FieldReader<u8, u8>;
84#[doc = "Field `l1c_bmx_arb_mode` writer - "]
85pub type L1C_BMX_ARB_MODE_W<'a, const O: u8> =
86 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 2, O>;
87#[doc = "Field `l1c_bmx_timeout_en` reader - "]
88pub type L1C_BMX_TIMEOUT_EN_R = crate::FieldReader<u8, u8>;
89#[doc = "Field `l1c_bmx_timeout_en` writer - "]
90pub type L1C_BMX_TIMEOUT_EN_W<'a, const O: u8> =
91 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 4, O>;
92#[doc = "Field `l1c_bmx_busy_option_dis` reader - "]
93pub type L1C_BMX_BUSY_OPTION_DIS_R = crate::BitReader<bool>;
94#[doc = "Field `l1c_bmx_busy_option_dis` writer - "]
95pub type L1C_BMX_BUSY_OPTION_DIS_W<'a, const O: u8> =
96 crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
97#[doc = "Field `early_resp_dis` reader - "]
98pub type EARLY_RESP_DIS_R = crate::BitReader<bool>;
99#[doc = "Field `early_resp_dis` writer - "]
100pub type EARLY_RESP_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
101#[doc = "Field `wrap_dis` reader - "]
102pub type WRAP_DIS_R = crate::BitReader<bool>;
103#[doc = "Field `wrap_dis` writer - "]
104pub type WRAP_DIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
105#[doc = "Field `l1c_flush_en` reader - "]
106pub type L1C_FLUSH_EN_R = crate::BitReader<bool>;
107#[doc = "Field `l1c_flush_en` writer - "]
108pub type L1C_FLUSH_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
109#[doc = "Field `l1c_flush_done` reader - "]
110pub type L1C_FLUSH_DONE_R = crate::BitReader<bool>;
111#[doc = "Field `l1c_flush_done` writer - "]
112pub type L1C_FLUSH_DONE_W<'a, const O: u8> = crate::BitWriter<'a, u32, L1C_CONFIG_SPEC, bool, O>;
113#[doc = "Field `reserved_31_30` reader - "]
114pub type RESERVED_31_30_R = crate::FieldReader<u8, u8>;
115#[doc = "Field `reserved_31_30` writer - "]
116pub type RESERVED_31_30_W<'a, const O: u8> =
117 crate::FieldWriter<'a, u32, L1C_CONFIG_SPEC, u8, u8, 2, O>;
118impl R {
119 #[doc = "Bit 0"]
120 #[inline(always)]
121 pub fn l1c_cacheable(&self) -> L1C_CACHEABLE_R {
122 L1C_CACHEABLE_R::new((self.bits & 1) != 0)
123 }
124 #[doc = "Bit 1"]
125 #[inline(always)]
126 pub fn l1c_cnt_en(&self) -> L1C_CNT_EN_R {
127 L1C_CNT_EN_R::new(((self.bits >> 1) & 1) != 0)
128 }
129 #[doc = "Bit 2"]
130 #[inline(always)]
131 pub fn l1c_invalid_en(&self) -> L1C_INVALID_EN_R {
132 L1C_INVALID_EN_R::new(((self.bits >> 2) & 1) != 0)
133 }
134 #[doc = "Bit 3"]
135 #[inline(always)]
136 pub fn l1c_invalid_done(&self) -> L1C_INVALID_DONE_R {
137 L1C_INVALID_DONE_R::new(((self.bits >> 3) & 1) != 0)
138 }
139 #[doc = "Bit 4"]
140 #[inline(always)]
141 pub fn l1c_wt_en(&self) -> L1C_WT_EN_R {
142 L1C_WT_EN_R::new(((self.bits >> 4) & 1) != 0)
143 }
144 #[doc = "Bit 5"]
145 #[inline(always)]
146 pub fn l1c_wb_en(&self) -> L1C_WB_EN_R {
147 L1C_WB_EN_R::new(((self.bits >> 5) & 1) != 0)
148 }
149 #[doc = "Bit 6"]
150 #[inline(always)]
151 pub fn l1c_wa_en(&self) -> L1C_WA_EN_R {
152 L1C_WA_EN_R::new(((self.bits >> 6) & 1) != 0)
153 }
154 #[doc = "Bits 8:11"]
155 #[inline(always)]
156 pub fn l1c_way_dis(&self) -> L1C_WAY_DIS_R {
157 L1C_WAY_DIS_R::new(((self.bits >> 8) & 0x0f) as u8)
158 }
159 #[doc = "Bit 12"]
160 #[inline(always)]
161 pub fn irom_2t_access(&self) -> IROM_2T_ACCESS_R {
162 IROM_2T_ACCESS_R::new(((self.bits >> 12) & 1) != 0)
163 }
164 #[doc = "Bit 14"]
165 #[inline(always)]
166 pub fn l1c_bypass(&self) -> L1C_BYPASS_R {
167 L1C_BYPASS_R::new(((self.bits >> 14) & 1) != 0)
168 }
169 #[doc = "Bit 15"]
170 #[inline(always)]
171 pub fn l1c_bmx_err_en(&self) -> L1C_BMX_ERR_EN_R {
172 L1C_BMX_ERR_EN_R::new(((self.bits >> 15) & 1) != 0)
173 }
174 #[doc = "Bits 16:17"]
175 #[inline(always)]
176 pub fn l1c_bmx_arb_mode(&self) -> L1C_BMX_ARB_MODE_R {
177 L1C_BMX_ARB_MODE_R::new(((self.bits >> 16) & 3) as u8)
178 }
179 #[doc = "Bits 20:23"]
180 #[inline(always)]
181 pub fn l1c_bmx_timeout_en(&self) -> L1C_BMX_TIMEOUT_EN_R {
182 L1C_BMX_TIMEOUT_EN_R::new(((self.bits >> 20) & 0x0f) as u8)
183 }
184 #[doc = "Bit 24"]
185 #[inline(always)]
186 pub fn l1c_bmx_busy_option_dis(&self) -> L1C_BMX_BUSY_OPTION_DIS_R {
187 L1C_BMX_BUSY_OPTION_DIS_R::new(((self.bits >> 24) & 1) != 0)
188 }
189 #[doc = "Bit 25"]
190 #[inline(always)]
191 pub fn early_resp_dis(&self) -> EARLY_RESP_DIS_R {
192 EARLY_RESP_DIS_R::new(((self.bits >> 25) & 1) != 0)
193 }
194 #[doc = "Bit 26"]
195 #[inline(always)]
196 pub fn wrap_dis(&self) -> WRAP_DIS_R {
197 WRAP_DIS_R::new(((self.bits >> 26) & 1) != 0)
198 }
199 #[doc = "Bit 28"]
200 #[inline(always)]
201 pub fn l1c_flush_en(&self) -> L1C_FLUSH_EN_R {
202 L1C_FLUSH_EN_R::new(((self.bits >> 28) & 1) != 0)
203 }
204 #[doc = "Bit 29"]
205 #[inline(always)]
206 pub fn l1c_flush_done(&self) -> L1C_FLUSH_DONE_R {
207 L1C_FLUSH_DONE_R::new(((self.bits >> 29) & 1) != 0)
208 }
209 #[doc = "Bits 30:31"]
210 #[inline(always)]
211 pub fn reserved_31_30(&self) -> RESERVED_31_30_R {
212 RESERVED_31_30_R::new(((self.bits >> 30) & 3) as u8)
213 }
214}
215impl W {
216 #[doc = "Bit 0"]
217 #[inline(always)]
218 #[must_use]
219 pub fn l1c_cacheable(&mut self) -> L1C_CACHEABLE_W<0> {
220 L1C_CACHEABLE_W::new(self)
221 }
222 #[doc = "Bit 1"]
223 #[inline(always)]
224 #[must_use]
225 pub fn l1c_cnt_en(&mut self) -> L1C_CNT_EN_W<1> {
226 L1C_CNT_EN_W::new(self)
227 }
228 #[doc = "Bit 2"]
229 #[inline(always)]
230 #[must_use]
231 pub fn l1c_invalid_en(&mut self) -> L1C_INVALID_EN_W<2> {
232 L1C_INVALID_EN_W::new(self)
233 }
234 #[doc = "Bit 3"]
235 #[inline(always)]
236 #[must_use]
237 pub fn l1c_invalid_done(&mut self) -> L1C_INVALID_DONE_W<3> {
238 L1C_INVALID_DONE_W::new(self)
239 }
240 #[doc = "Bit 4"]
241 #[inline(always)]
242 #[must_use]
243 pub fn l1c_wt_en(&mut self) -> L1C_WT_EN_W<4> {
244 L1C_WT_EN_W::new(self)
245 }
246 #[doc = "Bit 5"]
247 #[inline(always)]
248 #[must_use]
249 pub fn l1c_wb_en(&mut self) -> L1C_WB_EN_W<5> {
250 L1C_WB_EN_W::new(self)
251 }
252 #[doc = "Bit 6"]
253 #[inline(always)]
254 #[must_use]
255 pub fn l1c_wa_en(&mut self) -> L1C_WA_EN_W<6> {
256 L1C_WA_EN_W::new(self)
257 }
258 #[doc = "Bits 8:11"]
259 #[inline(always)]
260 #[must_use]
261 pub fn l1c_way_dis(&mut self) -> L1C_WAY_DIS_W<8> {
262 L1C_WAY_DIS_W::new(self)
263 }
264 #[doc = "Bit 12"]
265 #[inline(always)]
266 #[must_use]
267 pub fn irom_2t_access(&mut self) -> IROM_2T_ACCESS_W<12> {
268 IROM_2T_ACCESS_W::new(self)
269 }
270 #[doc = "Bit 14"]
271 #[inline(always)]
272 #[must_use]
273 pub fn l1c_bypass(&mut self) -> L1C_BYPASS_W<14> {
274 L1C_BYPASS_W::new(self)
275 }
276 #[doc = "Bit 15"]
277 #[inline(always)]
278 #[must_use]
279 pub fn l1c_bmx_err_en(&mut self) -> L1C_BMX_ERR_EN_W<15> {
280 L1C_BMX_ERR_EN_W::new(self)
281 }
282 #[doc = "Bits 16:17"]
283 #[inline(always)]
284 #[must_use]
285 pub fn l1c_bmx_arb_mode(&mut self) -> L1C_BMX_ARB_MODE_W<16> {
286 L1C_BMX_ARB_MODE_W::new(self)
287 }
288 #[doc = "Bits 20:23"]
289 #[inline(always)]
290 #[must_use]
291 pub fn l1c_bmx_timeout_en(&mut self) -> L1C_BMX_TIMEOUT_EN_W<20> {
292 L1C_BMX_TIMEOUT_EN_W::new(self)
293 }
294 #[doc = "Bit 24"]
295 #[inline(always)]
296 #[must_use]
297 pub fn l1c_bmx_busy_option_dis(&mut self) -> L1C_BMX_BUSY_OPTION_DIS_W<24> {
298 L1C_BMX_BUSY_OPTION_DIS_W::new(self)
299 }
300 #[doc = "Bit 25"]
301 #[inline(always)]
302 #[must_use]
303 pub fn early_resp_dis(&mut self) -> EARLY_RESP_DIS_W<25> {
304 EARLY_RESP_DIS_W::new(self)
305 }
306 #[doc = "Bit 26"]
307 #[inline(always)]
308 #[must_use]
309 pub fn wrap_dis(&mut self) -> WRAP_DIS_W<26> {
310 WRAP_DIS_W::new(self)
311 }
312 #[doc = "Bit 28"]
313 #[inline(always)]
314 #[must_use]
315 pub fn l1c_flush_en(&mut self) -> L1C_FLUSH_EN_W<28> {
316 L1C_FLUSH_EN_W::new(self)
317 }
318 #[doc = "Bit 29"]
319 #[inline(always)]
320 #[must_use]
321 pub fn l1c_flush_done(&mut self) -> L1C_FLUSH_DONE_W<29> {
322 L1C_FLUSH_DONE_W::new(self)
323 }
324 #[doc = "Bits 30:31"]
325 #[inline(always)]
326 #[must_use]
327 pub fn reserved_31_30(&mut self) -> RESERVED_31_30_W<30> {
328 RESERVED_31_30_W::new(self)
329 }
330 #[doc = "Writes raw bits to the register."]
331 #[inline(always)]
332 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
333 self.0.bits(bits);
334 self
335 }
336}
337#[doc = "l1c_config.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [l1c_config](index.html) module"]
338pub struct L1C_CONFIG_SPEC;
339impl crate::RegisterSpec for L1C_CONFIG_SPEC {
340 type Ux = u32;
341}
342#[doc = "`read()` method returns [l1c_config::R](R) reader structure"]
343impl crate::Readable for L1C_CONFIG_SPEC {
344 type Reader = R;
345}
346#[doc = "`write(|w| ..)` method takes [l1c_config::W](W) writer structure"]
347impl crate::Writable for L1C_CONFIG_SPEC {
348 type Writer = W;
349 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
350 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
351}
352#[doc = "`reset()` method sets l1c_config to value 0"]
353impl crate::Resettable for L1C_CONFIG_SPEC {
354 const RESET_VALUE: Self::Ux = 0;
355}