bl702_pac/sec_eng/
se_gmac_0_ctrl_0.rs1#[doc = "Register `se_gmac_0_ctrl_0` reader"]
2pub struct R(crate::R<SE_GMAC_0_CTRL_0_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SE_GMAC_0_CTRL_0_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SE_GMAC_0_CTRL_0_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SE_GMAC_0_CTRL_0_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `se_gmac_0_ctrl_0` writer"]
17pub struct W(crate::W<SE_GMAC_0_CTRL_0_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SE_GMAC_0_CTRL_0_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SE_GMAC_0_CTRL_0_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SE_GMAC_0_CTRL_0_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `se_gmac_0_busy` reader - "]
38pub type SE_GMAC_0_BUSY_R = crate::BitReader<bool>;
39#[doc = "Field `se_gmac_0_busy` writer - "]
40pub type SE_GMAC_0_BUSY_W<'a, const O: u8> =
41 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
42#[doc = "Field `se_gmac_0_trig_1t` reader - "]
43pub type SE_GMAC_0_TRIG_1T_R = crate::BitReader<bool>;
44#[doc = "Field `se_gmac_0_trig_1t` writer - "]
45pub type SE_GMAC_0_TRIG_1T_W<'a, const O: u8> =
46 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
47#[doc = "Field `se_gmac_0_en` reader - "]
48pub type SE_GMAC_0_EN_R = crate::BitReader<bool>;
49#[doc = "Field `se_gmac_0_en` writer - "]
50pub type SE_GMAC_0_EN_W<'a, const O: u8> =
51 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
52#[doc = "Field `se_gmac_0_int` reader - "]
53pub type SE_GMAC_0_INT_R = crate::BitReader<bool>;
54#[doc = "Field `se_gmac_0_int` writer - "]
55pub type SE_GMAC_0_INT_W<'a, const O: u8> =
56 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
57#[doc = "Field `se_gmac_0_int_clr_1t` reader - "]
58pub type SE_GMAC_0_INT_CLR_1T_R = crate::BitReader<bool>;
59#[doc = "Field `se_gmac_0_int_clr_1t` writer - "]
60pub type SE_GMAC_0_INT_CLR_1T_W<'a, const O: u8> =
61 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
62#[doc = "Field `se_gmac_0_int_set_1t` reader - "]
63pub type SE_GMAC_0_INT_SET_1T_R = crate::BitReader<bool>;
64#[doc = "Field `se_gmac_0_int_set_1t` writer - "]
65pub type SE_GMAC_0_INT_SET_1T_W<'a, const O: u8> =
66 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
67#[doc = "Field `se_gmac_0_int_mask` reader - "]
68pub type SE_GMAC_0_INT_MASK_R = crate::BitReader<bool>;
69#[doc = "Field `se_gmac_0_int_mask` writer - "]
70pub type SE_GMAC_0_INT_MASK_W<'a, const O: u8> =
71 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
72#[doc = "Field `se_gmac_0_t_endian` reader - "]
73pub type SE_GMAC_0_T_ENDIAN_R = crate::BitReader<bool>;
74#[doc = "Field `se_gmac_0_t_endian` writer - "]
75pub type SE_GMAC_0_T_ENDIAN_W<'a, const O: u8> =
76 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
77#[doc = "Field `se_gmac_0_h_endian` reader - "]
78pub type SE_GMAC_0_H_ENDIAN_R = crate::BitReader<bool>;
79#[doc = "Field `se_gmac_0_h_endian` writer - "]
80pub type SE_GMAC_0_H_ENDIAN_W<'a, const O: u8> =
81 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
82#[doc = "Field `se_gmac_0_x_endian` reader - "]
83pub type SE_GMAC_0_X_ENDIAN_R = crate::BitReader<bool>;
84#[doc = "Field `se_gmac_0_x_endian` writer - "]
85pub type SE_GMAC_0_X_ENDIAN_W<'a, const O: u8> =
86 crate::BitWriter<'a, u32, SE_GMAC_0_CTRL_0_SPEC, bool, O>;
87impl R {
88 #[doc = "Bit 0"]
89 #[inline(always)]
90 pub fn se_gmac_0_busy(&self) -> SE_GMAC_0_BUSY_R {
91 SE_GMAC_0_BUSY_R::new((self.bits & 1) != 0)
92 }
93 #[doc = "Bit 1"]
94 #[inline(always)]
95 pub fn se_gmac_0_trig_1t(&self) -> SE_GMAC_0_TRIG_1T_R {
96 SE_GMAC_0_TRIG_1T_R::new(((self.bits >> 1) & 1) != 0)
97 }
98 #[doc = "Bit 2"]
99 #[inline(always)]
100 pub fn se_gmac_0_en(&self) -> SE_GMAC_0_EN_R {
101 SE_GMAC_0_EN_R::new(((self.bits >> 2) & 1) != 0)
102 }
103 #[doc = "Bit 8"]
104 #[inline(always)]
105 pub fn se_gmac_0_int(&self) -> SE_GMAC_0_INT_R {
106 SE_GMAC_0_INT_R::new(((self.bits >> 8) & 1) != 0)
107 }
108 #[doc = "Bit 9"]
109 #[inline(always)]
110 pub fn se_gmac_0_int_clr_1t(&self) -> SE_GMAC_0_INT_CLR_1T_R {
111 SE_GMAC_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
112 }
113 #[doc = "Bit 10"]
114 #[inline(always)]
115 pub fn se_gmac_0_int_set_1t(&self) -> SE_GMAC_0_INT_SET_1T_R {
116 SE_GMAC_0_INT_SET_1T_R::new(((self.bits >> 10) & 1) != 0)
117 }
118 #[doc = "Bit 11"]
119 #[inline(always)]
120 pub fn se_gmac_0_int_mask(&self) -> SE_GMAC_0_INT_MASK_R {
121 SE_GMAC_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
122 }
123 #[doc = "Bit 12"]
124 #[inline(always)]
125 pub fn se_gmac_0_t_endian(&self) -> SE_GMAC_0_T_ENDIAN_R {
126 SE_GMAC_0_T_ENDIAN_R::new(((self.bits >> 12) & 1) != 0)
127 }
128 #[doc = "Bit 13"]
129 #[inline(always)]
130 pub fn se_gmac_0_h_endian(&self) -> SE_GMAC_0_H_ENDIAN_R {
131 SE_GMAC_0_H_ENDIAN_R::new(((self.bits >> 13) & 1) != 0)
132 }
133 #[doc = "Bit 14"]
134 #[inline(always)]
135 pub fn se_gmac_0_x_endian(&self) -> SE_GMAC_0_X_ENDIAN_R {
136 SE_GMAC_0_X_ENDIAN_R::new(((self.bits >> 14) & 1) != 0)
137 }
138}
139impl W {
140 #[doc = "Bit 0"]
141 #[inline(always)]
142 #[must_use]
143 pub fn se_gmac_0_busy(&mut self) -> SE_GMAC_0_BUSY_W<0> {
144 SE_GMAC_0_BUSY_W::new(self)
145 }
146 #[doc = "Bit 1"]
147 #[inline(always)]
148 #[must_use]
149 pub fn se_gmac_0_trig_1t(&mut self) -> SE_GMAC_0_TRIG_1T_W<1> {
150 SE_GMAC_0_TRIG_1T_W::new(self)
151 }
152 #[doc = "Bit 2"]
153 #[inline(always)]
154 #[must_use]
155 pub fn se_gmac_0_en(&mut self) -> SE_GMAC_0_EN_W<2> {
156 SE_GMAC_0_EN_W::new(self)
157 }
158 #[doc = "Bit 8"]
159 #[inline(always)]
160 #[must_use]
161 pub fn se_gmac_0_int(&mut self) -> SE_GMAC_0_INT_W<8> {
162 SE_GMAC_0_INT_W::new(self)
163 }
164 #[doc = "Bit 9"]
165 #[inline(always)]
166 #[must_use]
167 pub fn se_gmac_0_int_clr_1t(&mut self) -> SE_GMAC_0_INT_CLR_1T_W<9> {
168 SE_GMAC_0_INT_CLR_1T_W::new(self)
169 }
170 #[doc = "Bit 10"]
171 #[inline(always)]
172 #[must_use]
173 pub fn se_gmac_0_int_set_1t(&mut self) -> SE_GMAC_0_INT_SET_1T_W<10> {
174 SE_GMAC_0_INT_SET_1T_W::new(self)
175 }
176 #[doc = "Bit 11"]
177 #[inline(always)]
178 #[must_use]
179 pub fn se_gmac_0_int_mask(&mut self) -> SE_GMAC_0_INT_MASK_W<11> {
180 SE_GMAC_0_INT_MASK_W::new(self)
181 }
182 #[doc = "Bit 12"]
183 #[inline(always)]
184 #[must_use]
185 pub fn se_gmac_0_t_endian(&mut self) -> SE_GMAC_0_T_ENDIAN_W<12> {
186 SE_GMAC_0_T_ENDIAN_W::new(self)
187 }
188 #[doc = "Bit 13"]
189 #[inline(always)]
190 #[must_use]
191 pub fn se_gmac_0_h_endian(&mut self) -> SE_GMAC_0_H_ENDIAN_W<13> {
192 SE_GMAC_0_H_ENDIAN_W::new(self)
193 }
194 #[doc = "Bit 14"]
195 #[inline(always)]
196 #[must_use]
197 pub fn se_gmac_0_x_endian(&mut self) -> SE_GMAC_0_X_ENDIAN_W<14> {
198 SE_GMAC_0_X_ENDIAN_W::new(self)
199 }
200 #[doc = "Writes raw bits to the register."]
201 #[inline(always)]
202 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
203 self.0.bits(bits);
204 self
205 }
206}
207#[doc = "se_gmac_0_ctrl_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_gmac_0_ctrl_0](index.html) module"]
208pub struct SE_GMAC_0_CTRL_0_SPEC;
209impl crate::RegisterSpec for SE_GMAC_0_CTRL_0_SPEC {
210 type Ux = u32;
211}
212#[doc = "`read()` method returns [se_gmac_0_ctrl_0::R](R) reader structure"]
213impl crate::Readable for SE_GMAC_0_CTRL_0_SPEC {
214 type Reader = R;
215}
216#[doc = "`write(|w| ..)` method takes [se_gmac_0_ctrl_0::W](W) writer structure"]
217impl crate::Writable for SE_GMAC_0_CTRL_0_SPEC {
218 type Writer = W;
219 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
220 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
221}
222#[doc = "`reset()` method sets se_gmac_0_ctrl_0 to value 0"]
223impl crate::Resettable for SE_GMAC_0_CTRL_0_SPEC {
224 const RESET_VALUE: Self::Ux = 0;
225}