1#[doc = "Register `se_aes_0_ctrl` reader"]
2pub struct R(crate::R<SE_AES_0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SE_AES_0_CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SE_AES_0_CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SE_AES_0_CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `se_aes_0_ctrl` writer"]
17pub struct W(crate::W<SE_AES_0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SE_AES_0_CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SE_AES_0_CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SE_AES_0_CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `se_aes_0_busy` reader - "]
38pub type SE_AES_0_BUSY_R = crate::BitReader<bool>;
39#[doc = "Field `se_aes_0_busy` writer - "]
40pub type SE_AES_0_BUSY_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
41#[doc = "Field `se_aes_0_trig_1t` reader - "]
42pub type SE_AES_0_TRIG_1T_R = crate::BitReader<bool>;
43#[doc = "Field `se_aes_0_trig_1t` writer - "]
44pub type SE_AES_0_TRIG_1T_W<'a, const O: u8> =
45 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
46#[doc = "Field `se_aes_0_en` reader - "]
47pub type SE_AES_0_EN_R = crate::BitReader<bool>;
48#[doc = "Field `se_aes_0_en` writer - "]
49pub type SE_AES_0_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
50#[doc = "Field `se_aes_0_mode` reader - "]
51pub type SE_AES_0_MODE_R = crate::FieldReader<u8, u8>;
52#[doc = "Field `se_aes_0_mode` writer - "]
53pub type SE_AES_0_MODE_W<'a, const O: u8> =
54 crate::FieldWriter<'a, u32, SE_AES_0_CTRL_SPEC, u8, u8, 2, O>;
55#[doc = "Field `se_aes_0_dec_en` reader - "]
56pub type SE_AES_0_DEC_EN_R = crate::BitReader<bool>;
57#[doc = "Field `se_aes_0_dec_en` writer - "]
58pub type SE_AES_0_DEC_EN_W<'a, const O: u8> =
59 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
60#[doc = "Field `se_aes_0_dec_key_sel` reader - "]
61pub type SE_AES_0_DEC_KEY_SEL_R = crate::BitReader<bool>;
62#[doc = "Field `se_aes_0_dec_key_sel` writer - "]
63pub type SE_AES_0_DEC_KEY_SEL_W<'a, const O: u8> =
64 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
65#[doc = "Field `se_aes_0_hw_key_en` reader - "]
66pub type SE_AES_0_HW_KEY_EN_R = crate::BitReader<bool>;
67#[doc = "Field `se_aes_0_hw_key_en` writer - "]
68pub type SE_AES_0_HW_KEY_EN_W<'a, const O: u8> =
69 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
70#[doc = "Field `se_aes_0_int` reader - "]
71pub type SE_AES_0_INT_R = crate::BitReader<bool>;
72#[doc = "Field `se_aes_0_int` writer - "]
73pub type SE_AES_0_INT_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
74#[doc = "Field `se_aes_0_int_clr_1t` reader - "]
75pub type SE_AES_0_INT_CLR_1T_R = crate::BitReader<bool>;
76#[doc = "Field `se_aes_0_int_clr_1t` writer - "]
77pub type SE_AES_0_INT_CLR_1T_W<'a, const O: u8> =
78 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
79#[doc = "Field `se_aes_0_int_set_1t` reader - "]
80pub type SE_AES_0_INT_SET_1T_R = crate::BitReader<bool>;
81#[doc = "Field `se_aes_0_int_set_1t` writer - "]
82pub type SE_AES_0_INT_SET_1T_W<'a, const O: u8> =
83 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
84#[doc = "Field `se_aes_0_int_mask` reader - "]
85pub type SE_AES_0_INT_MASK_R = crate::BitReader<bool>;
86#[doc = "Field `se_aes_0_int_mask` writer - "]
87pub type SE_AES_0_INT_MASK_W<'a, const O: u8> =
88 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
89#[doc = "Field `se_aes_0_block_mode` reader - "]
90pub type SE_AES_0_BLOCK_MODE_R = crate::FieldReader<u8, u8>;
91#[doc = "Field `se_aes_0_block_mode` writer - "]
92pub type SE_AES_0_BLOCK_MODE_W<'a, const O: u8> =
93 crate::FieldWriter<'a, u32, SE_AES_0_CTRL_SPEC, u8, u8, 2, O>;
94#[doc = "Field `se_aes_0_iv_sel` reader - "]
95pub type SE_AES_0_IV_SEL_R = crate::BitReader<bool>;
96#[doc = "Field `se_aes_0_iv_sel` writer - "]
97pub type SE_AES_0_IV_SEL_W<'a, const O: u8> =
98 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
99#[doc = "Field `se_aes_0_link_mode` reader - "]
100pub type SE_AES_0_LINK_MODE_R = crate::BitReader<bool>;
101#[doc = "Field `se_aes_0_link_mode` writer - "]
102pub type SE_AES_0_LINK_MODE_W<'a, const O: u8> =
103 crate::BitWriter<'a, u32, SE_AES_0_CTRL_SPEC, bool, O>;
104#[doc = "Field `se_aes_0_msg_len` reader - "]
105pub type SE_AES_0_MSG_LEN_R = crate::FieldReader<u16, u16>;
106#[doc = "Field `se_aes_0_msg_len` writer - "]
107pub type SE_AES_0_MSG_LEN_W<'a, const O: u8> =
108 crate::FieldWriter<'a, u32, SE_AES_0_CTRL_SPEC, u16, u16, 16, O>;
109impl R {
110 #[doc = "Bit 0"]
111 #[inline(always)]
112 pub fn se_aes_0_busy(&self) -> SE_AES_0_BUSY_R {
113 SE_AES_0_BUSY_R::new((self.bits & 1) != 0)
114 }
115 #[doc = "Bit 1"]
116 #[inline(always)]
117 pub fn se_aes_0_trig_1t(&self) -> SE_AES_0_TRIG_1T_R {
118 SE_AES_0_TRIG_1T_R::new(((self.bits >> 1) & 1) != 0)
119 }
120 #[doc = "Bit 2"]
121 #[inline(always)]
122 pub fn se_aes_0_en(&self) -> SE_AES_0_EN_R {
123 SE_AES_0_EN_R::new(((self.bits >> 2) & 1) != 0)
124 }
125 #[doc = "Bits 3:4"]
126 #[inline(always)]
127 pub fn se_aes_0_mode(&self) -> SE_AES_0_MODE_R {
128 SE_AES_0_MODE_R::new(((self.bits >> 3) & 3) as u8)
129 }
130 #[doc = "Bit 5"]
131 #[inline(always)]
132 pub fn se_aes_0_dec_en(&self) -> SE_AES_0_DEC_EN_R {
133 SE_AES_0_DEC_EN_R::new(((self.bits >> 5) & 1) != 0)
134 }
135 #[doc = "Bit 6"]
136 #[inline(always)]
137 pub fn se_aes_0_dec_key_sel(&self) -> SE_AES_0_DEC_KEY_SEL_R {
138 SE_AES_0_DEC_KEY_SEL_R::new(((self.bits >> 6) & 1) != 0)
139 }
140 #[doc = "Bit 7"]
141 #[inline(always)]
142 pub fn se_aes_0_hw_key_en(&self) -> SE_AES_0_HW_KEY_EN_R {
143 SE_AES_0_HW_KEY_EN_R::new(((self.bits >> 7) & 1) != 0)
144 }
145 #[doc = "Bit 8"]
146 #[inline(always)]
147 pub fn se_aes_0_int(&self) -> SE_AES_0_INT_R {
148 SE_AES_0_INT_R::new(((self.bits >> 8) & 1) != 0)
149 }
150 #[doc = "Bit 9"]
151 #[inline(always)]
152 pub fn se_aes_0_int_clr_1t(&self) -> SE_AES_0_INT_CLR_1T_R {
153 SE_AES_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
154 }
155 #[doc = "Bit 10"]
156 #[inline(always)]
157 pub fn se_aes_0_int_set_1t(&self) -> SE_AES_0_INT_SET_1T_R {
158 SE_AES_0_INT_SET_1T_R::new(((self.bits >> 10) & 1) != 0)
159 }
160 #[doc = "Bit 11"]
161 #[inline(always)]
162 pub fn se_aes_0_int_mask(&self) -> SE_AES_0_INT_MASK_R {
163 SE_AES_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
164 }
165 #[doc = "Bits 12:13"]
166 #[inline(always)]
167 pub fn se_aes_0_block_mode(&self) -> SE_AES_0_BLOCK_MODE_R {
168 SE_AES_0_BLOCK_MODE_R::new(((self.bits >> 12) & 3) as u8)
169 }
170 #[doc = "Bit 14"]
171 #[inline(always)]
172 pub fn se_aes_0_iv_sel(&self) -> SE_AES_0_IV_SEL_R {
173 SE_AES_0_IV_SEL_R::new(((self.bits >> 14) & 1) != 0)
174 }
175 #[doc = "Bit 15"]
176 #[inline(always)]
177 pub fn se_aes_0_link_mode(&self) -> SE_AES_0_LINK_MODE_R {
178 SE_AES_0_LINK_MODE_R::new(((self.bits >> 15) & 1) != 0)
179 }
180 #[doc = "Bits 16:31"]
181 #[inline(always)]
182 pub fn se_aes_0_msg_len(&self) -> SE_AES_0_MSG_LEN_R {
183 SE_AES_0_MSG_LEN_R::new(((self.bits >> 16) & 0xffff) as u16)
184 }
185}
186impl W {
187 #[doc = "Bit 0"]
188 #[inline(always)]
189 #[must_use]
190 pub fn se_aes_0_busy(&mut self) -> SE_AES_0_BUSY_W<0> {
191 SE_AES_0_BUSY_W::new(self)
192 }
193 #[doc = "Bit 1"]
194 #[inline(always)]
195 #[must_use]
196 pub fn se_aes_0_trig_1t(&mut self) -> SE_AES_0_TRIG_1T_W<1> {
197 SE_AES_0_TRIG_1T_W::new(self)
198 }
199 #[doc = "Bit 2"]
200 #[inline(always)]
201 #[must_use]
202 pub fn se_aes_0_en(&mut self) -> SE_AES_0_EN_W<2> {
203 SE_AES_0_EN_W::new(self)
204 }
205 #[doc = "Bits 3:4"]
206 #[inline(always)]
207 #[must_use]
208 pub fn se_aes_0_mode(&mut self) -> SE_AES_0_MODE_W<3> {
209 SE_AES_0_MODE_W::new(self)
210 }
211 #[doc = "Bit 5"]
212 #[inline(always)]
213 #[must_use]
214 pub fn se_aes_0_dec_en(&mut self) -> SE_AES_0_DEC_EN_W<5> {
215 SE_AES_0_DEC_EN_W::new(self)
216 }
217 #[doc = "Bit 6"]
218 #[inline(always)]
219 #[must_use]
220 pub fn se_aes_0_dec_key_sel(&mut self) -> SE_AES_0_DEC_KEY_SEL_W<6> {
221 SE_AES_0_DEC_KEY_SEL_W::new(self)
222 }
223 #[doc = "Bit 7"]
224 #[inline(always)]
225 #[must_use]
226 pub fn se_aes_0_hw_key_en(&mut self) -> SE_AES_0_HW_KEY_EN_W<7> {
227 SE_AES_0_HW_KEY_EN_W::new(self)
228 }
229 #[doc = "Bit 8"]
230 #[inline(always)]
231 #[must_use]
232 pub fn se_aes_0_int(&mut self) -> SE_AES_0_INT_W<8> {
233 SE_AES_0_INT_W::new(self)
234 }
235 #[doc = "Bit 9"]
236 #[inline(always)]
237 #[must_use]
238 pub fn se_aes_0_int_clr_1t(&mut self) -> SE_AES_0_INT_CLR_1T_W<9> {
239 SE_AES_0_INT_CLR_1T_W::new(self)
240 }
241 #[doc = "Bit 10"]
242 #[inline(always)]
243 #[must_use]
244 pub fn se_aes_0_int_set_1t(&mut self) -> SE_AES_0_INT_SET_1T_W<10> {
245 SE_AES_0_INT_SET_1T_W::new(self)
246 }
247 #[doc = "Bit 11"]
248 #[inline(always)]
249 #[must_use]
250 pub fn se_aes_0_int_mask(&mut self) -> SE_AES_0_INT_MASK_W<11> {
251 SE_AES_0_INT_MASK_W::new(self)
252 }
253 #[doc = "Bits 12:13"]
254 #[inline(always)]
255 #[must_use]
256 pub fn se_aes_0_block_mode(&mut self) -> SE_AES_0_BLOCK_MODE_W<12> {
257 SE_AES_0_BLOCK_MODE_W::new(self)
258 }
259 #[doc = "Bit 14"]
260 #[inline(always)]
261 #[must_use]
262 pub fn se_aes_0_iv_sel(&mut self) -> SE_AES_0_IV_SEL_W<14> {
263 SE_AES_0_IV_SEL_W::new(self)
264 }
265 #[doc = "Bit 15"]
266 #[inline(always)]
267 #[must_use]
268 pub fn se_aes_0_link_mode(&mut self) -> SE_AES_0_LINK_MODE_W<15> {
269 SE_AES_0_LINK_MODE_W::new(self)
270 }
271 #[doc = "Bits 16:31"]
272 #[inline(always)]
273 #[must_use]
274 pub fn se_aes_0_msg_len(&mut self) -> SE_AES_0_MSG_LEN_W<16> {
275 SE_AES_0_MSG_LEN_W::new(self)
276 }
277 #[doc = "Writes raw bits to the register."]
278 #[inline(always)]
279 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
280 self.0.bits(bits);
281 self
282 }
283}
284#[doc = "se_aes_0_ctrl.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_aes_0_ctrl](index.html) module"]
285pub struct SE_AES_0_CTRL_SPEC;
286impl crate::RegisterSpec for SE_AES_0_CTRL_SPEC {
287 type Ux = u32;
288}
289#[doc = "`read()` method returns [se_aes_0_ctrl::R](R) reader structure"]
290impl crate::Readable for SE_AES_0_CTRL_SPEC {
291 type Reader = R;
292}
293#[doc = "`write(|w| ..)` method takes [se_aes_0_ctrl::W](W) writer structure"]
294impl crate::Writable for SE_AES_0_CTRL_SPEC {
295 type Writer = W;
296 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
297 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
298}
299#[doc = "`reset()` method sets se_aes_0_ctrl to value 0"]
300impl crate::Resettable for SE_AES_0_CTRL_SPEC {
301 const RESET_VALUE: Self::Ux = 0;
302}