1#[doc = "Register `fbdv` reader"]
2pub struct R(crate::R<FBDV_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<FBDV_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<FBDV_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<FBDV_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `fbdv` writer"]
17pub struct W(crate::W<FBDV_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<FBDV_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<FBDV_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<FBDV_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `fbdv_tpm_clk_sel` reader - "]
38pub type FBDV_TPM_CLK_SEL_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `fbdv_tpm_clk_sel` writer - "]
40pub type FBDV_TPM_CLK_SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FBDV_SPEC, u8, u8, 3, O>;
41#[doc = "Field `fbdv_adpll_clk_sel` reader - "]
42pub type FBDV_ADPLL_CLK_SEL_R = crate::BitReader<bool>;
43#[doc = "Field `fbdv_adpll_clk_sel` writer - "]
44pub type FBDV_ADPLL_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
45#[doc = "Field `fbdv_dco_dither_clk_sel` reader - "]
46pub type FBDV_DCO_DITHER_CLK_SEL_R = crate::BitReader<bool>;
47#[doc = "Field `fbdv_dco_dither_clk_sel` writer - "]
48pub type FBDV_DCO_DITHER_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
49#[doc = "Field `fbdv_fb_clk_sel` reader - "]
50pub type FBDV_FB_CLK_SEL_R = crate::BitReader<bool>;
51#[doc = "Field `fbdv_fb_clk_sel` writer - "]
52pub type FBDV_FB_CLK_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
53#[doc = "Field `fbdv_sample_clk_sel` reader - "]
54pub type FBDV_SAMPLE_CLK_SEL_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `fbdv_sample_clk_sel` writer - "]
56pub type FBDV_SAMPLE_CLK_SEL_W<'a, const O: u8> =
57 crate::FieldWriter<'a, u32, FBDV_SPEC, u8, u8, 2, O>;
58#[doc = "Field `fbdv_stg_sel` reader - "]
59pub type FBDV_STG_SEL_R = crate::BitReader<bool>;
60#[doc = "Field `fbdv_stg_sel` writer - "]
61pub type FBDV_STG_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
62#[doc = "Field `rst_mmdiv` reader - "]
63pub type RST_MMDIV_R = crate::BitReader<bool>;
64#[doc = "Field `rst_mmdiv` writer - "]
65pub type RST_MMDIV_W<'a, const O: u8> = crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
66#[doc = "Field `lotpm_fmash_clk_polarity` reader - "]
67pub type LOTPM_FMASH_CLK_POLARITY_R = crate::BitReader<bool>;
68#[doc = "Field `lotpm_fmash_clk_polarity` writer - "]
69pub type LOTPM_FMASH_CLK_POLARITY_W<'a, const O: u8> =
70 crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
71#[doc = "Field `dco_dither_clk_polarity` reader - "]
72pub type DCO_DITHER_CLK_POLARITY_R = crate::BitReader<bool>;
73#[doc = "Field `dco_dither_clk_polarity` writer - "]
74pub type DCO_DITHER_CLK_POLARITY_W<'a, const O: u8> = crate::BitWriter<'a, u32, FBDV_SPEC, bool, O>;
75impl R {
76 #[doc = "Bits 0:2"]
77 #[inline(always)]
78 pub fn fbdv_tpm_clk_sel(&self) -> FBDV_TPM_CLK_SEL_R {
79 FBDV_TPM_CLK_SEL_R::new((self.bits & 7) as u8)
80 }
81 #[doc = "Bit 4"]
82 #[inline(always)]
83 pub fn fbdv_adpll_clk_sel(&self) -> FBDV_ADPLL_CLK_SEL_R {
84 FBDV_ADPLL_CLK_SEL_R::new(((self.bits >> 4) & 1) != 0)
85 }
86 #[doc = "Bit 8"]
87 #[inline(always)]
88 pub fn fbdv_dco_dither_clk_sel(&self) -> FBDV_DCO_DITHER_CLK_SEL_R {
89 FBDV_DCO_DITHER_CLK_SEL_R::new(((self.bits >> 8) & 1) != 0)
90 }
91 #[doc = "Bit 12"]
92 #[inline(always)]
93 pub fn fbdv_fb_clk_sel(&self) -> FBDV_FB_CLK_SEL_R {
94 FBDV_FB_CLK_SEL_R::new(((self.bits >> 12) & 1) != 0)
95 }
96 #[doc = "Bits 16:17"]
97 #[inline(always)]
98 pub fn fbdv_sample_clk_sel(&self) -> FBDV_SAMPLE_CLK_SEL_R {
99 FBDV_SAMPLE_CLK_SEL_R::new(((self.bits >> 16) & 3) as u8)
100 }
101 #[doc = "Bit 20"]
102 #[inline(always)]
103 pub fn fbdv_stg_sel(&self) -> FBDV_STG_SEL_R {
104 FBDV_STG_SEL_R::new(((self.bits >> 20) & 1) != 0)
105 }
106 #[doc = "Bit 24"]
107 #[inline(always)]
108 pub fn rst_mmdiv(&self) -> RST_MMDIV_R {
109 RST_MMDIV_R::new(((self.bits >> 24) & 1) != 0)
110 }
111 #[doc = "Bit 28"]
112 #[inline(always)]
113 pub fn lotpm_fmash_clk_polarity(&self) -> LOTPM_FMASH_CLK_POLARITY_R {
114 LOTPM_FMASH_CLK_POLARITY_R::new(((self.bits >> 28) & 1) != 0)
115 }
116 #[doc = "Bit 29"]
117 #[inline(always)]
118 pub fn dco_dither_clk_polarity(&self) -> DCO_DITHER_CLK_POLARITY_R {
119 DCO_DITHER_CLK_POLARITY_R::new(((self.bits >> 29) & 1) != 0)
120 }
121}
122impl W {
123 #[doc = "Bits 0:2"]
124 #[inline(always)]
125 #[must_use]
126 pub fn fbdv_tpm_clk_sel(&mut self) -> FBDV_TPM_CLK_SEL_W<0> {
127 FBDV_TPM_CLK_SEL_W::new(self)
128 }
129 #[doc = "Bit 4"]
130 #[inline(always)]
131 #[must_use]
132 pub fn fbdv_adpll_clk_sel(&mut self) -> FBDV_ADPLL_CLK_SEL_W<4> {
133 FBDV_ADPLL_CLK_SEL_W::new(self)
134 }
135 #[doc = "Bit 8"]
136 #[inline(always)]
137 #[must_use]
138 pub fn fbdv_dco_dither_clk_sel(&mut self) -> FBDV_DCO_DITHER_CLK_SEL_W<8> {
139 FBDV_DCO_DITHER_CLK_SEL_W::new(self)
140 }
141 #[doc = "Bit 12"]
142 #[inline(always)]
143 #[must_use]
144 pub fn fbdv_fb_clk_sel(&mut self) -> FBDV_FB_CLK_SEL_W<12> {
145 FBDV_FB_CLK_SEL_W::new(self)
146 }
147 #[doc = "Bits 16:17"]
148 #[inline(always)]
149 #[must_use]
150 pub fn fbdv_sample_clk_sel(&mut self) -> FBDV_SAMPLE_CLK_SEL_W<16> {
151 FBDV_SAMPLE_CLK_SEL_W::new(self)
152 }
153 #[doc = "Bit 20"]
154 #[inline(always)]
155 #[must_use]
156 pub fn fbdv_stg_sel(&mut self) -> FBDV_STG_SEL_W<20> {
157 FBDV_STG_SEL_W::new(self)
158 }
159 #[doc = "Bit 24"]
160 #[inline(always)]
161 #[must_use]
162 pub fn rst_mmdiv(&mut self) -> RST_MMDIV_W<24> {
163 RST_MMDIV_W::new(self)
164 }
165 #[doc = "Bit 28"]
166 #[inline(always)]
167 #[must_use]
168 pub fn lotpm_fmash_clk_polarity(&mut self) -> LOTPM_FMASH_CLK_POLARITY_W<28> {
169 LOTPM_FMASH_CLK_POLARITY_W::new(self)
170 }
171 #[doc = "Bit 29"]
172 #[inline(always)]
173 #[must_use]
174 pub fn dco_dither_clk_polarity(&mut self) -> DCO_DITHER_CLK_POLARITY_W<29> {
175 DCO_DITHER_CLK_POLARITY_W::new(self)
176 }
177 #[doc = "Writes raw bits to the register."]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180 self.0.bits(bits);
181 self
182 }
183}
184#[doc = "fbdv.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbdv](index.html) module"]
185pub struct FBDV_SPEC;
186impl crate::RegisterSpec for FBDV_SPEC {
187 type Ux = u32;
188}
189#[doc = "`read()` method returns [fbdv::R](R) reader structure"]
190impl crate::Readable for FBDV_SPEC {
191 type Reader = R;
192}
193#[doc = "`write(|w| ..)` method takes [fbdv::W](W) writer structure"]
194impl crate::Writable for FBDV_SPEC {
195 type Writer = W;
196 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
197 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
198}
199#[doc = "`reset()` method sets fbdv to value 0"]
200impl crate::Resettable for FBDV_SPEC {
201 const RESET_VALUE: Self::Ux = 0;
202}