bl702_pac/glb/
cpu_clk_cfg.rs

1#[doc = "Register `CPU_CLK_CFG` reader"]
2pub struct R(crate::R<CPU_CLK_CFG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CPU_CLK_CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CPU_CLK_CFG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CPU_CLK_CFG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CPU_CLK_CFG` writer"]
17pub struct W(crate::W<CPU_CLK_CFG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CPU_CLK_CFG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CPU_CLK_CFG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CPU_CLK_CFG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `cpu_rtc_div` reader - "]
38pub type CPU_RTC_DIV_R = crate::FieldReader<u32, u32>;
39#[doc = "Field `cpu_rtc_div` writer - "]
40pub type CPU_RTC_DIV_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, CPU_CLK_CFG_SPEC, u32, u32, 17, O>;
42#[doc = "Field `cpu_rtc_en` reader - "]
43pub type CPU_RTC_EN_R = crate::BitReader<bool>;
44#[doc = "Field `cpu_rtc_en` writer - "]
45pub type CPU_RTC_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CPU_CLK_CFG_SPEC, bool, O>;
46#[doc = "Field `cpu_rtc_sel` reader - "]
47pub type CPU_RTC_SEL_R = crate::BitReader<bool>;
48#[doc = "Field `cpu_rtc_sel` writer - "]
49pub type CPU_RTC_SEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CPU_CLK_CFG_SPEC, bool, O>;
50#[doc = "Field `debug_ndreset_gate` reader - "]
51pub type DEBUG_NDRESET_GATE_R = crate::BitReader<bool>;
52#[doc = "Field `debug_ndreset_gate` writer - "]
53pub type DEBUG_NDRESET_GATE_W<'a, const O: u8> =
54    crate::BitWriter<'a, u32, CPU_CLK_CFG_SPEC, bool, O>;
55impl R {
56    #[doc = "Bits 0:16"]
57    #[inline(always)]
58    pub fn cpu_rtc_div(&self) -> CPU_RTC_DIV_R {
59        CPU_RTC_DIV_R::new(self.bits & 0x0001_ffff)
60    }
61    #[doc = "Bit 18"]
62    #[inline(always)]
63    pub fn cpu_rtc_en(&self) -> CPU_RTC_EN_R {
64        CPU_RTC_EN_R::new(((self.bits >> 18) & 1) != 0)
65    }
66    #[doc = "Bit 19"]
67    #[inline(always)]
68    pub fn cpu_rtc_sel(&self) -> CPU_RTC_SEL_R {
69        CPU_RTC_SEL_R::new(((self.bits >> 19) & 1) != 0)
70    }
71    #[doc = "Bit 20"]
72    #[inline(always)]
73    pub fn debug_ndreset_gate(&self) -> DEBUG_NDRESET_GATE_R {
74        DEBUG_NDRESET_GATE_R::new(((self.bits >> 20) & 1) != 0)
75    }
76}
77impl W {
78    #[doc = "Bits 0:16"]
79    #[inline(always)]
80    #[must_use]
81    pub fn cpu_rtc_div(&mut self) -> CPU_RTC_DIV_W<0> {
82        CPU_RTC_DIV_W::new(self)
83    }
84    #[doc = "Bit 18"]
85    #[inline(always)]
86    #[must_use]
87    pub fn cpu_rtc_en(&mut self) -> CPU_RTC_EN_W<18> {
88        CPU_RTC_EN_W::new(self)
89    }
90    #[doc = "Bit 19"]
91    #[inline(always)]
92    #[must_use]
93    pub fn cpu_rtc_sel(&mut self) -> CPU_RTC_SEL_W<19> {
94        CPU_RTC_SEL_W::new(self)
95    }
96    #[doc = "Bit 20"]
97    #[inline(always)]
98    #[must_use]
99    pub fn debug_ndreset_gate(&mut self) -> DEBUG_NDRESET_GATE_W<20> {
100        DEBUG_NDRESET_GATE_W::new(self)
101    }
102    #[doc = "Writes raw bits to the register."]
103    #[inline(always)]
104    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
105        self.0.bits(bits);
106        self
107    }
108}
109#[doc = "CPU_CLK_CFG.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpu_clk_cfg](index.html) module"]
110pub struct CPU_CLK_CFG_SPEC;
111impl crate::RegisterSpec for CPU_CLK_CFG_SPEC {
112    type Ux = u32;
113}
114#[doc = "`read()` method returns [cpu_clk_cfg::R](R) reader structure"]
115impl crate::Readable for CPU_CLK_CFG_SPEC {
116    type Reader = R;
117}
118#[doc = "`write(|w| ..)` method takes [cpu_clk_cfg::W](W) writer structure"]
119impl crate::Writable for CPU_CLK_CFG_SPEC {
120    type Writer = W;
121    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
122    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123}
124#[doc = "`reset()` method sets CPU_CLK_CFG to value 0"]
125impl crate::Resettable for CPU_CLK_CFG_SPEC {
126    const RESET_VALUE: Self::Ux = 0;
127}
bl702_pac/glb/cpu_clk_cfg.rs

bl702_pac/glb/
cpu_clk_cfg.rs
