1#[doc = "Register `DMA_C4Control` reader"]
2pub struct R(crate::R<DMA_C4CONTROL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DMA_C4CONTROL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DMA_C4CONTROL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DMA_C4CONTROL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `DMA_C4Control` writer"]
17pub struct W(crate::W<DMA_C4CONTROL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<DMA_C4CONTROL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<DMA_C4CONTROL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<DMA_C4CONTROL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `TransferSize` reader - "]
38pub type TRANSFER_SIZE_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `TransferSize` writer - "]
40pub type TRANSFER_SIZE_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u16, u16, 12, O>;
42#[doc = "Field `SBSize` reader - "]
43pub type SBSIZE_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `SBSize` writer - "]
45pub type SBSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u8, u8, 2, O>;
46#[doc = "Field `dst_min_mode` reader - "]
47pub type DST_MIN_MODE_R = crate::BitReader<bool>;
48#[doc = "Field `dst_min_mode` writer - "]
49pub type DST_MIN_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_C4CONTROL_SPEC, bool, O>;
50#[doc = "Field `DBSize` reader - "]
51pub type DBSIZE_R = crate::FieldReader<u8, u8>;
52#[doc = "Field `DBSize` writer - "]
53pub type DBSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u8, u8, 2, O>;
54#[doc = "Field `dst_add_mode` reader - "]
55pub type DST_ADD_MODE_R = crate::BitReader<bool>;
56#[doc = "Field `dst_add_mode` writer - "]
57pub type DST_ADD_MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_C4CONTROL_SPEC, bool, O>;
58#[doc = "Field `SWidth` reader - "]
59pub type SWIDTH_R = crate::FieldReader<u8, u8>;
60#[doc = "Field `SWidth` writer - "]
61pub type SWIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u8, u8, 3, O>;
62#[doc = "Field `DWidth` reader - "]
63pub type DWIDTH_R = crate::FieldReader<u8, u8>;
64#[doc = "Field `DWidth` writer - "]
65pub type DWIDTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u8, u8, 3, O>;
66#[doc = "Field `fix_cnt` reader - "]
67pub type FIX_CNT_R = crate::FieldReader<u8, u8>;
68#[doc = "Field `fix_cnt` writer - "]
69pub type FIX_CNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u8, u8, 2, O>;
70#[doc = "Field `SI` reader - "]
71pub type SI_R = crate::BitReader<bool>;
72#[doc = "Field `SI` writer - "]
73pub type SI_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_C4CONTROL_SPEC, bool, O>;
74#[doc = "Field `DI` reader - "]
75pub type DI_R = crate::BitReader<bool>;
76#[doc = "Field `DI` writer - "]
77pub type DI_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_C4CONTROL_SPEC, bool, O>;
78#[doc = "Field `Prot` reader - "]
79pub type PROT_R = crate::FieldReader<u8, u8>;
80#[doc = "Field `Prot` writer - "]
81pub type PROT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA_C4CONTROL_SPEC, u8, u8, 3, O>;
82#[doc = "Field `I` reader - "]
83pub type I_R = crate::BitReader<bool>;
84#[doc = "Field `I` writer - "]
85pub type I_W<'a, const O: u8> = crate::BitWriter<'a, u32, DMA_C4CONTROL_SPEC, bool, O>;
86impl R {
87 #[doc = "Bits 0:11"]
88 #[inline(always)]
89 pub fn transfer_size(&self) -> TRANSFER_SIZE_R {
90 TRANSFER_SIZE_R::new((self.bits & 0x0fff) as u16)
91 }
92 #[doc = "Bits 12:13"]
93 #[inline(always)]
94 pub fn sbsize(&self) -> SBSIZE_R {
95 SBSIZE_R::new(((self.bits >> 12) & 3) as u8)
96 }
97 #[doc = "Bit 14"]
98 #[inline(always)]
99 pub fn dst_min_mode(&self) -> DST_MIN_MODE_R {
100 DST_MIN_MODE_R::new(((self.bits >> 14) & 1) != 0)
101 }
102 #[doc = "Bits 15:16"]
103 #[inline(always)]
104 pub fn dbsize(&self) -> DBSIZE_R {
105 DBSIZE_R::new(((self.bits >> 15) & 3) as u8)
106 }
107 #[doc = "Bit 17"]
108 #[inline(always)]
109 pub fn dst_add_mode(&self) -> DST_ADD_MODE_R {
110 DST_ADD_MODE_R::new(((self.bits >> 17) & 1) != 0)
111 }
112 #[doc = "Bits 18:20"]
113 #[inline(always)]
114 pub fn swidth(&self) -> SWIDTH_R {
115 SWIDTH_R::new(((self.bits >> 18) & 7) as u8)
116 }
117 #[doc = "Bits 21:23"]
118 #[inline(always)]
119 pub fn dwidth(&self) -> DWIDTH_R {
120 DWIDTH_R::new(((self.bits >> 21) & 7) as u8)
121 }
122 #[doc = "Bits 23:24"]
123 #[inline(always)]
124 pub fn fix_cnt(&self) -> FIX_CNT_R {
125 FIX_CNT_R::new(((self.bits >> 23) & 3) as u8)
126 }
127 #[doc = "Bit 26"]
128 #[inline(always)]
129 pub fn si(&self) -> SI_R {
130 SI_R::new(((self.bits >> 26) & 1) != 0)
131 }
132 #[doc = "Bit 27"]
133 #[inline(always)]
134 pub fn di(&self) -> DI_R {
135 DI_R::new(((self.bits >> 27) & 1) != 0)
136 }
137 #[doc = "Bits 28:30"]
138 #[inline(always)]
139 pub fn prot(&self) -> PROT_R {
140 PROT_R::new(((self.bits >> 28) & 7) as u8)
141 }
142 #[doc = "Bit 31"]
143 #[inline(always)]
144 pub fn i(&self) -> I_R {
145 I_R::new(((self.bits >> 31) & 1) != 0)
146 }
147}
148impl W {
149 #[doc = "Bits 0:11"]
150 #[inline(always)]
151 #[must_use]
152 pub fn transfer_size(&mut self) -> TRANSFER_SIZE_W<0> {
153 TRANSFER_SIZE_W::new(self)
154 }
155 #[doc = "Bits 12:13"]
156 #[inline(always)]
157 #[must_use]
158 pub fn sbsize(&mut self) -> SBSIZE_W<12> {
159 SBSIZE_W::new(self)
160 }
161 #[doc = "Bit 14"]
162 #[inline(always)]
163 #[must_use]
164 pub fn dst_min_mode(&mut self) -> DST_MIN_MODE_W<14> {
165 DST_MIN_MODE_W::new(self)
166 }
167 #[doc = "Bits 15:16"]
168 #[inline(always)]
169 #[must_use]
170 pub fn dbsize(&mut self) -> DBSIZE_W<15> {
171 DBSIZE_W::new(self)
172 }
173 #[doc = "Bit 17"]
174 #[inline(always)]
175 #[must_use]
176 pub fn dst_add_mode(&mut self) -> DST_ADD_MODE_W<17> {
177 DST_ADD_MODE_W::new(self)
178 }
179 #[doc = "Bits 18:20"]
180 #[inline(always)]
181 #[must_use]
182 pub fn swidth(&mut self) -> SWIDTH_W<18> {
183 SWIDTH_W::new(self)
184 }
185 #[doc = "Bits 21:23"]
186 #[inline(always)]
187 #[must_use]
188 pub fn dwidth(&mut self) -> DWIDTH_W<21> {
189 DWIDTH_W::new(self)
190 }
191 #[doc = "Bits 23:24"]
192 #[inline(always)]
193 #[must_use]
194 pub fn fix_cnt(&mut self) -> FIX_CNT_W<23> {
195 FIX_CNT_W::new(self)
196 }
197 #[doc = "Bit 26"]
198 #[inline(always)]
199 #[must_use]
200 pub fn si(&mut self) -> SI_W<26> {
201 SI_W::new(self)
202 }
203 #[doc = "Bit 27"]
204 #[inline(always)]
205 #[must_use]
206 pub fn di(&mut self) -> DI_W<27> {
207 DI_W::new(self)
208 }
209 #[doc = "Bits 28:30"]
210 #[inline(always)]
211 #[must_use]
212 pub fn prot(&mut self) -> PROT_W<28> {
213 PROT_W::new(self)
214 }
215 #[doc = "Bit 31"]
216 #[inline(always)]
217 #[must_use]
218 pub fn i(&mut self) -> I_W<31> {
219 I_W::new(self)
220 }
221 #[doc = "Writes raw bits to the register."]
222 #[inline(always)]
223 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
224 self.0.bits(bits);
225 self
226 }
227}
228#[doc = "DMA_C4Control.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_c4control](index.html) module"]
229pub struct DMA_C4CONTROL_SPEC;
230impl crate::RegisterSpec for DMA_C4CONTROL_SPEC {
231 type Ux = u32;
232}
233#[doc = "`read()` method returns [dma_c4control::R](R) reader structure"]
234impl crate::Readable for DMA_C4CONTROL_SPEC {
235 type Reader = R;
236}
237#[doc = "`write(|w| ..)` method takes [dma_c4control::W](W) writer structure"]
238impl crate::Writable for DMA_C4CONTROL_SPEC {
239 type Writer = W;
240 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
241 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
242}
243#[doc = "`reset()` method sets DMA_C4Control to value 0"]
244impl crate::Resettable for DMA_C4CONTROL_SPEC {
245 const RESET_VALUE: Self::Ux = 0;
246}