bl61x_pac/pds/
pds_ctl.rs

1#[doc = "Register `PDS_CTL` reader"]
2pub type R = crate::R<PDS_CTL_SPEC>;
3#[doc = "Register `PDS_CTL` writer"]
4pub type W = crate::W<PDS_CTL_SPEC>;
5#[doc = "Field `pds_start_ps` reader - "]
6pub type PDS_START_PS_R = crate::BitReader;
7#[doc = "Field `pds_start_ps` writer - "]
8pub type PDS_START_PS_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `cr_sleep_forever` reader - "]
10pub type CR_SLEEP_FOREVER_R = crate::BitReader;
11#[doc = "Field `cr_sleep_forever` writer - "]
12pub type CR_SLEEP_FOREVER_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `cr_xtal_force_off` reader - "]
14pub type CR_XTAL_FORCE_OFF_R = crate::BitReader;
15#[doc = "Field `cr_xtal_force_off` writer - "]
16pub type CR_XTAL_FORCE_OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `cr_pds_wifi_save_state` reader - "]
18pub type CR_PDS_WIFI_SAVE_STATE_R = crate::BitReader;
19#[doc = "Field `cr_pds_wifi_save_state` writer - "]
20pub type CR_PDS_WIFI_SAVE_STATE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `cr_pds_pd_ldo11` reader - "]
22pub type CR_PDS_PD_LDO11_R = crate::BitReader;
23#[doc = "Field `cr_pds_pd_ldo11` writer - "]
24pub type CR_PDS_PD_LDO11_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `cr_pds_pd_bg_sys` reader - "]
26pub type CR_PDS_PD_BG_SYS_R = crate::BitReader;
27#[doc = "Field `cr_pds_pd_bg_sys` writer - "]
28pub type CR_PDS_PD_BG_SYS_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `cr_pds_ctrl_gpio_ie_pu_pd` reader - "]
30pub type CR_PDS_CTRL_GPIO_IE_PU_PD_R = crate::BitReader;
31#[doc = "Field `cr_pds_ctrl_gpio_ie_pu_pd` writer - "]
32pub type CR_PDS_CTRL_GPIO_IE_PU_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `cr_pds_pd_dcdc18` reader - "]
34pub type CR_PDS_PD_DCDC18_R = crate::BitReader;
35#[doc = "Field `cr_pds_pd_dcdc18` writer - "]
36pub type CR_PDS_PD_DCDC18_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `cr_pds_gate_clk` reader - "]
38pub type CR_PDS_GATE_CLK_R = crate::BitReader;
39#[doc = "Field `cr_pds_gate_clk` writer - "]
40pub type CR_PDS_GATE_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `cr_pds_mem_stby` reader - "]
42pub type CR_PDS_MEM_STBY_R = crate::BitReader;
43#[doc = "Field `cr_pds_mem_stby` writer - "]
44pub type CR_PDS_MEM_STBY_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `cr_pds_glb_reg_reset_protect` reader - "]
46pub type CR_PDS_GLB_REG_RESET_PROTECT_R = crate::BitReader;
47#[doc = "Field `cr_pds_glb_reg_reset_protect` writer - "]
48pub type CR_PDS_GLB_REG_RESET_PROTECT_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `cr_pds_iso_en` reader - "]
50pub type CR_PDS_ISO_EN_R = crate::BitReader;
51#[doc = "Field `cr_pds_iso_en` writer - "]
52pub type CR_PDS_ISO_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `cr_pds_wait_xtal_rdy` reader - "]
54pub type CR_PDS_WAIT_XTAL_RDY_R = crate::BitReader;
55#[doc = "Field `cr_pds_wait_xtal_rdy` writer - "]
56pub type CR_PDS_WAIT_XTAL_RDY_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `cr_pds_pwr_off` reader - "]
58pub type CR_PDS_PWR_OFF_R = crate::BitReader;
59#[doc = "Field `cr_pds_pwr_off` writer - "]
60pub type CR_PDS_PWR_OFF_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `cr_pds_pd_xtal` reader - "]
62pub type CR_PDS_PD_XTAL_R = crate::BitReader;
63#[doc = "Field `cr_pds_pd_xtal` writer - "]
64pub type CR_PDS_PD_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `cr_pds_ctrl_soc_enb` reader - "]
66pub type CR_PDS_CTRL_SOC_ENB_R = crate::BitReader;
67#[doc = "Field `cr_pds_ctrl_soc_enb` writer - "]
68pub type CR_PDS_CTRL_SOC_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `cr_pds_rst_soc` reader - "]
70pub type CR_PDS_RST_SOC_R = crate::BitReader;
71#[doc = "Field `cr_pds_rst_soc` writer - "]
72pub type CR_PDS_RST_SOC_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `cr_pds_rc32m_off_dis` reader - "]
74pub type CR_PDS_RC32M_OFF_DIS_R = crate::BitReader;
75#[doc = "Field `cr_pds_rc32m_off_dis` writer - "]
76pub type CR_PDS_RC32M_OFF_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `cr_pds_ldo11_vsel_en` reader - "]
78pub type CR_PDS_LDO11_VSEL_EN_R = crate::BitReader;
79#[doc = "Field `cr_pds_ldo11_vsel_en` writer - "]
80pub type CR_PDS_LDO11_VSEL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `cr_pds_ctrl_usbpll_pd` reader - "]
82pub type CR_PDS_CTRL_USBPLL_PD_R = crate::BitReader;
83#[doc = "Field `cr_pds_ctrl_usbpll_pd` writer - "]
84pub type CR_PDS_CTRL_USBPLL_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `cr_pds_ctrl_aupll_pd` reader - "]
86pub type CR_PDS_CTRL_AUPLL_PD_R = crate::BitReader;
87#[doc = "Field `cr_pds_ctrl_aupll_pd` writer - "]
88pub type CR_PDS_CTRL_AUPLL_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `cr_pds_ctrl_wifipll_pd` reader - "]
90pub type CR_PDS_CTRL_WIFIPLL_PD_R = crate::BitReader;
91#[doc = "Field `cr_pds_ctrl_wifipll_pd` writer - "]
92pub type CR_PDS_CTRL_WIFIPLL_PD_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `cr_pds_ldo11_vol` reader - "]
94pub type CR_PDS_LDO11_VOL_R = crate::FieldReader;
95#[doc = "Field `cr_pds_ldo11_vol` writer - "]
96pub type CR_PDS_LDO11_VOL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
97#[doc = "Field `cr_pds_ctrl_rf` reader - "]
98pub type CR_PDS_CTRL_RF_R = crate::FieldReader;
99#[doc = "Field `cr_pds_ctrl_rf` writer - "]
100pub type CR_PDS_CTRL_RF_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
101#[doc = "Field `cr_pds_start_use_tbtt_sleep` reader - "]
102pub type CR_PDS_START_USE_TBTT_SLEEP_R = crate::BitReader;
103#[doc = "Field `cr_pds_start_use_tbtt_sleep` writer - "]
104pub type CR_PDS_START_USE_TBTT_SLEEP_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `cr_pds_gpio_iso_mode` reader - "]
106pub type CR_PDS_GPIO_ISO_MODE_R = crate::BitReader;
107#[doc = "Field `cr_pds_gpio_iso_mode` writer - "]
108pub type CR_PDS_GPIO_ISO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
109impl R {
110    #[doc = "Bit 0"]
111    #[inline(always)]
112    pub fn pds_start_ps(&self) -> PDS_START_PS_R {
113        PDS_START_PS_R::new((self.bits & 1) != 0)
114    }
115    #[doc = "Bit 1"]
116    #[inline(always)]
117    pub fn cr_sleep_forever(&self) -> CR_SLEEP_FOREVER_R {
118        CR_SLEEP_FOREVER_R::new(((self.bits >> 1) & 1) != 0)
119    }
120    #[doc = "Bit 2"]
121    #[inline(always)]
122    pub fn cr_xtal_force_off(&self) -> CR_XTAL_FORCE_OFF_R {
123        CR_XTAL_FORCE_OFF_R::new(((self.bits >> 2) & 1) != 0)
124    }
125    #[doc = "Bit 3"]
126    #[inline(always)]
127    pub fn cr_pds_wifi_save_state(&self) -> CR_PDS_WIFI_SAVE_STATE_R {
128        CR_PDS_WIFI_SAVE_STATE_R::new(((self.bits >> 3) & 1) != 0)
129    }
130    #[doc = "Bit 4"]
131    #[inline(always)]
132    pub fn cr_pds_pd_ldo11(&self) -> CR_PDS_PD_LDO11_R {
133        CR_PDS_PD_LDO11_R::new(((self.bits >> 4) & 1) != 0)
134    }
135    #[doc = "Bit 5"]
136    #[inline(always)]
137    pub fn cr_pds_pd_bg_sys(&self) -> CR_PDS_PD_BG_SYS_R {
138        CR_PDS_PD_BG_SYS_R::new(((self.bits >> 5) & 1) != 0)
139    }
140    #[doc = "Bit 6"]
141    #[inline(always)]
142    pub fn cr_pds_ctrl_gpio_ie_pu_pd(&self) -> CR_PDS_CTRL_GPIO_IE_PU_PD_R {
143        CR_PDS_CTRL_GPIO_IE_PU_PD_R::new(((self.bits >> 6) & 1) != 0)
144    }
145    #[doc = "Bit 7"]
146    #[inline(always)]
147    pub fn cr_pds_pd_dcdc18(&self) -> CR_PDS_PD_DCDC18_R {
148        CR_PDS_PD_DCDC18_R::new(((self.bits >> 7) & 1) != 0)
149    }
150    #[doc = "Bit 8"]
151    #[inline(always)]
152    pub fn cr_pds_gate_clk(&self) -> CR_PDS_GATE_CLK_R {
153        CR_PDS_GATE_CLK_R::new(((self.bits >> 8) & 1) != 0)
154    }
155    #[doc = "Bit 9"]
156    #[inline(always)]
157    pub fn cr_pds_mem_stby(&self) -> CR_PDS_MEM_STBY_R {
158        CR_PDS_MEM_STBY_R::new(((self.bits >> 9) & 1) != 0)
159    }
160    #[doc = "Bit 10"]
161    #[inline(always)]
162    pub fn cr_pds_glb_reg_reset_protect(&self) -> CR_PDS_GLB_REG_RESET_PROTECT_R {
163        CR_PDS_GLB_REG_RESET_PROTECT_R::new(((self.bits >> 10) & 1) != 0)
164    }
165    #[doc = "Bit 11"]
166    #[inline(always)]
167    pub fn cr_pds_iso_en(&self) -> CR_PDS_ISO_EN_R {
168        CR_PDS_ISO_EN_R::new(((self.bits >> 11) & 1) != 0)
169    }
170    #[doc = "Bit 12"]
171    #[inline(always)]
172    pub fn cr_pds_wait_xtal_rdy(&self) -> CR_PDS_WAIT_XTAL_RDY_R {
173        CR_PDS_WAIT_XTAL_RDY_R::new(((self.bits >> 12) & 1) != 0)
174    }
175    #[doc = "Bit 13"]
176    #[inline(always)]
177    pub fn cr_pds_pwr_off(&self) -> CR_PDS_PWR_OFF_R {
178        CR_PDS_PWR_OFF_R::new(((self.bits >> 13) & 1) != 0)
179    }
180    #[doc = "Bit 14"]
181    #[inline(always)]
182    pub fn cr_pds_pd_xtal(&self) -> CR_PDS_PD_XTAL_R {
183        CR_PDS_PD_XTAL_R::new(((self.bits >> 14) & 1) != 0)
184    }
185    #[doc = "Bit 15"]
186    #[inline(always)]
187    pub fn cr_pds_ctrl_soc_enb(&self) -> CR_PDS_CTRL_SOC_ENB_R {
188        CR_PDS_CTRL_SOC_ENB_R::new(((self.bits >> 15) & 1) != 0)
189    }
190    #[doc = "Bit 16"]
191    #[inline(always)]
192    pub fn cr_pds_rst_soc(&self) -> CR_PDS_RST_SOC_R {
193        CR_PDS_RST_SOC_R::new(((self.bits >> 16) & 1) != 0)
194    }
195    #[doc = "Bit 17"]
196    #[inline(always)]
197    pub fn cr_pds_rc32m_off_dis(&self) -> CR_PDS_RC32M_OFF_DIS_R {
198        CR_PDS_RC32M_OFF_DIS_R::new(((self.bits >> 17) & 1) != 0)
199    }
200    #[doc = "Bit 18"]
201    #[inline(always)]
202    pub fn cr_pds_ldo11_vsel_en(&self) -> CR_PDS_LDO11_VSEL_EN_R {
203        CR_PDS_LDO11_VSEL_EN_R::new(((self.bits >> 18) & 1) != 0)
204    }
205    #[doc = "Bit 19"]
206    #[inline(always)]
207    pub fn cr_pds_ctrl_usbpll_pd(&self) -> CR_PDS_CTRL_USBPLL_PD_R {
208        CR_PDS_CTRL_USBPLL_PD_R::new(((self.bits >> 19) & 1) != 0)
209    }
210    #[doc = "Bit 20"]
211    #[inline(always)]
212    pub fn cr_pds_ctrl_aupll_pd(&self) -> CR_PDS_CTRL_AUPLL_PD_R {
213        CR_PDS_CTRL_AUPLL_PD_R::new(((self.bits >> 20) & 1) != 0)
214    }
215    #[doc = "Bit 22"]
216    #[inline(always)]
217    pub fn cr_pds_ctrl_wifipll_pd(&self) -> CR_PDS_CTRL_WIFIPLL_PD_R {
218        CR_PDS_CTRL_WIFIPLL_PD_R::new(((self.bits >> 22) & 1) != 0)
219    }
220    #[doc = "Bits 23:27"]
221    #[inline(always)]
222    pub fn cr_pds_ldo11_vol(&self) -> CR_PDS_LDO11_VOL_R {
223        CR_PDS_LDO11_VOL_R::new(((self.bits >> 23) & 0x1f) as u8)
224    }
225    #[doc = "Bits 28:29"]
226    #[inline(always)]
227    pub fn cr_pds_ctrl_rf(&self) -> CR_PDS_CTRL_RF_R {
228        CR_PDS_CTRL_RF_R::new(((self.bits >> 28) & 3) as u8)
229    }
230    #[doc = "Bit 30"]
231    #[inline(always)]
232    pub fn cr_pds_start_use_tbtt_sleep(&self) -> CR_PDS_START_USE_TBTT_SLEEP_R {
233        CR_PDS_START_USE_TBTT_SLEEP_R::new(((self.bits >> 30) & 1) != 0)
234    }
235    #[doc = "Bit 31"]
236    #[inline(always)]
237    pub fn cr_pds_gpio_iso_mode(&self) -> CR_PDS_GPIO_ISO_MODE_R {
238        CR_PDS_GPIO_ISO_MODE_R::new(((self.bits >> 31) & 1) != 0)
239    }
240}
241impl W {
242    #[doc = "Bit 0"]
243    #[inline(always)]
244    #[must_use]
245    pub fn pds_start_ps(&mut self) -> PDS_START_PS_W<PDS_CTL_SPEC> {
246        PDS_START_PS_W::new(self, 0)
247    }
248    #[doc = "Bit 1"]
249    #[inline(always)]
250    #[must_use]
251    pub fn cr_sleep_forever(&mut self) -> CR_SLEEP_FOREVER_W<PDS_CTL_SPEC> {
252        CR_SLEEP_FOREVER_W::new(self, 1)
253    }
254    #[doc = "Bit 2"]
255    #[inline(always)]
256    #[must_use]
257    pub fn cr_xtal_force_off(&mut self) -> CR_XTAL_FORCE_OFF_W<PDS_CTL_SPEC> {
258        CR_XTAL_FORCE_OFF_W::new(self, 2)
259    }
260    #[doc = "Bit 3"]
261    #[inline(always)]
262    #[must_use]
263    pub fn cr_pds_wifi_save_state(&mut self) -> CR_PDS_WIFI_SAVE_STATE_W<PDS_CTL_SPEC> {
264        CR_PDS_WIFI_SAVE_STATE_W::new(self, 3)
265    }
266    #[doc = "Bit 4"]
267    #[inline(always)]
268    #[must_use]
269    pub fn cr_pds_pd_ldo11(&mut self) -> CR_PDS_PD_LDO11_W<PDS_CTL_SPEC> {
270        CR_PDS_PD_LDO11_W::new(self, 4)
271    }
272    #[doc = "Bit 5"]
273    #[inline(always)]
274    #[must_use]
275    pub fn cr_pds_pd_bg_sys(&mut self) -> CR_PDS_PD_BG_SYS_W<PDS_CTL_SPEC> {
276        CR_PDS_PD_BG_SYS_W::new(self, 5)
277    }
278    #[doc = "Bit 6"]
279    #[inline(always)]
280    #[must_use]
281    pub fn cr_pds_ctrl_gpio_ie_pu_pd(&mut self) -> CR_PDS_CTRL_GPIO_IE_PU_PD_W<PDS_CTL_SPEC> {
282        CR_PDS_CTRL_GPIO_IE_PU_PD_W::new(self, 6)
283    }
284    #[doc = "Bit 7"]
285    #[inline(always)]
286    #[must_use]
287    pub fn cr_pds_pd_dcdc18(&mut self) -> CR_PDS_PD_DCDC18_W<PDS_CTL_SPEC> {
288        CR_PDS_PD_DCDC18_W::new(self, 7)
289    }
290    #[doc = "Bit 8"]
291    #[inline(always)]
292    #[must_use]
293    pub fn cr_pds_gate_clk(&mut self) -> CR_PDS_GATE_CLK_W<PDS_CTL_SPEC> {
294        CR_PDS_GATE_CLK_W::new(self, 8)
295    }
296    #[doc = "Bit 9"]
297    #[inline(always)]
298    #[must_use]
299    pub fn cr_pds_mem_stby(&mut self) -> CR_PDS_MEM_STBY_W<PDS_CTL_SPEC> {
300        CR_PDS_MEM_STBY_W::new(self, 9)
301    }
302    #[doc = "Bit 10"]
303    #[inline(always)]
304    #[must_use]
305    pub fn cr_pds_glb_reg_reset_protect(&mut self) -> CR_PDS_GLB_REG_RESET_PROTECT_W<PDS_CTL_SPEC> {
306        CR_PDS_GLB_REG_RESET_PROTECT_W::new(self, 10)
307    }
308    #[doc = "Bit 11"]
309    #[inline(always)]
310    #[must_use]
311    pub fn cr_pds_iso_en(&mut self) -> CR_PDS_ISO_EN_W<PDS_CTL_SPEC> {
312        CR_PDS_ISO_EN_W::new(self, 11)
313    }
314    #[doc = "Bit 12"]
315    #[inline(always)]
316    #[must_use]
317    pub fn cr_pds_wait_xtal_rdy(&mut self) -> CR_PDS_WAIT_XTAL_RDY_W<PDS_CTL_SPEC> {
318        CR_PDS_WAIT_XTAL_RDY_W::new(self, 12)
319    }
320    #[doc = "Bit 13"]
321    #[inline(always)]
322    #[must_use]
323    pub fn cr_pds_pwr_off(&mut self) -> CR_PDS_PWR_OFF_W<PDS_CTL_SPEC> {
324        CR_PDS_PWR_OFF_W::new(self, 13)
325    }
326    #[doc = "Bit 14"]
327    #[inline(always)]
328    #[must_use]
329    pub fn cr_pds_pd_xtal(&mut self) -> CR_PDS_PD_XTAL_W<PDS_CTL_SPEC> {
330        CR_PDS_PD_XTAL_W::new(self, 14)
331    }
332    #[doc = "Bit 15"]
333    #[inline(always)]
334    #[must_use]
335    pub fn cr_pds_ctrl_soc_enb(&mut self) -> CR_PDS_CTRL_SOC_ENB_W<PDS_CTL_SPEC> {
336        CR_PDS_CTRL_SOC_ENB_W::new(self, 15)
337    }
338    #[doc = "Bit 16"]
339    #[inline(always)]
340    #[must_use]
341    pub fn cr_pds_rst_soc(&mut self) -> CR_PDS_RST_SOC_W<PDS_CTL_SPEC> {
342        CR_PDS_RST_SOC_W::new(self, 16)
343    }
344    #[doc = "Bit 17"]
345    #[inline(always)]
346    #[must_use]
347    pub fn cr_pds_rc32m_off_dis(&mut self) -> CR_PDS_RC32M_OFF_DIS_W<PDS_CTL_SPEC> {
348        CR_PDS_RC32M_OFF_DIS_W::new(self, 17)
349    }
350    #[doc = "Bit 18"]
351    #[inline(always)]
352    #[must_use]
353    pub fn cr_pds_ldo11_vsel_en(&mut self) -> CR_PDS_LDO11_VSEL_EN_W<PDS_CTL_SPEC> {
354        CR_PDS_LDO11_VSEL_EN_W::new(self, 18)
355    }
356    #[doc = "Bit 19"]
357    #[inline(always)]
358    #[must_use]
359    pub fn cr_pds_ctrl_usbpll_pd(&mut self) -> CR_PDS_CTRL_USBPLL_PD_W<PDS_CTL_SPEC> {
360        CR_PDS_CTRL_USBPLL_PD_W::new(self, 19)
361    }
362    #[doc = "Bit 20"]
363    #[inline(always)]
364    #[must_use]
365    pub fn cr_pds_ctrl_aupll_pd(&mut self) -> CR_PDS_CTRL_AUPLL_PD_W<PDS_CTL_SPEC> {
366        CR_PDS_CTRL_AUPLL_PD_W::new(self, 20)
367    }
368    #[doc = "Bit 22"]
369    #[inline(always)]
370    #[must_use]
371    pub fn cr_pds_ctrl_wifipll_pd(&mut self) -> CR_PDS_CTRL_WIFIPLL_PD_W<PDS_CTL_SPEC> {
372        CR_PDS_CTRL_WIFIPLL_PD_W::new(self, 22)
373    }
374    #[doc = "Bits 23:27"]
375    #[inline(always)]
376    #[must_use]
377    pub fn cr_pds_ldo11_vol(&mut self) -> CR_PDS_LDO11_VOL_W<PDS_CTL_SPEC> {
378        CR_PDS_LDO11_VOL_W::new(self, 23)
379    }
380    #[doc = "Bits 28:29"]
381    #[inline(always)]
382    #[must_use]
383    pub fn cr_pds_ctrl_rf(&mut self) -> CR_PDS_CTRL_RF_W<PDS_CTL_SPEC> {
384        CR_PDS_CTRL_RF_W::new(self, 28)
385    }
386    #[doc = "Bit 30"]
387    #[inline(always)]
388    #[must_use]
389    pub fn cr_pds_start_use_tbtt_sleep(&mut self) -> CR_PDS_START_USE_TBTT_SLEEP_W<PDS_CTL_SPEC> {
390        CR_PDS_START_USE_TBTT_SLEEP_W::new(self, 30)
391    }
392    #[doc = "Bit 31"]
393    #[inline(always)]
394    #[must_use]
395    pub fn cr_pds_gpio_iso_mode(&mut self) -> CR_PDS_GPIO_ISO_MODE_W<PDS_CTL_SPEC> {
396        CR_PDS_GPIO_ISO_MODE_W::new(self, 31)
397    }
398    #[doc = r" Writes raw bits to the register."]
399    #[doc = r""]
400    #[doc = r" # Safety"]
401    #[doc = r""]
402    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
403    #[inline(always)]
404    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
405        self.bits = bits;
406        self
407    }
408}
409#[doc = "PDS_CTL.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pds_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pds_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
410pub struct PDS_CTL_SPEC;
411impl crate::RegisterSpec for PDS_CTL_SPEC {
412    type Ux = u32;
413}
414#[doc = "`read()` method returns [`pds_ctl::R`](R) reader structure"]
415impl crate::Readable for PDS_CTL_SPEC {}
416#[doc = "`write(|w| ..)` method takes [`pds_ctl::W`](W) writer structure"]
417impl crate::Writable for PDS_CTL_SPEC {
418    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
419    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
420}
421#[doc = "`reset()` method sets PDS_CTL to value 0"]
422impl crate::Resettable for PDS_CTL_SPEC {
423    const RESET_VALUE: Self::Ux = 0;
424}