bl61x_pac/i2s/
fifo_config_0.rs

1#[doc = "Register `fifo_config_0` reader"]
2pub type R = crate::R<FIFO_CONFIG_0_SPEC>;
3#[doc = "Register `fifo_config_0` writer"]
4pub type W = crate::W<FIFO_CONFIG_0_SPEC>;
5#[doc = "Field `transmit_dma` reader - Enable signal of transmit DMA interface"]
6pub use RECEIVE_DMA_R as TRANSMIT_DMA_R;
7#[doc = "Field `transmit_dma` writer - Enable signal of transmit DMA interface"]
8pub use RECEIVE_DMA_W as TRANSMIT_DMA_W;
9#[doc = "Field `receive_dma` reader - Enable signal of receive DMA interface"]
10pub type RECEIVE_DMA_R = crate::BitReader<DMA_ENABLE_A>;
11#[doc = "Enable signal of receive DMA interface\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum DMA_ENABLE_A {
14    #[doc = "1: Enable DMA interface"]
15    ENABLE = 1,
16    #[doc = "0: Disable DMA interface"]
17    DISABLE = 0,
18}
19impl From<DMA_ENABLE_A> for bool {
20    #[inline(always)]
21    fn from(variant: DMA_ENABLE_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl RECEIVE_DMA_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> DMA_ENABLE_A {
29        match self.bits {
30            true => DMA_ENABLE_A::ENABLE,
31            false => DMA_ENABLE_A::DISABLE,
32        }
33    }
34    #[doc = "Enable DMA interface"]
35    #[inline(always)]
36    pub fn is_enable(&self) -> bool {
37        *self == DMA_ENABLE_A::ENABLE
38    }
39    #[doc = "Disable DMA interface"]
40    #[inline(always)]
41    pub fn is_disable(&self) -> bool {
42        *self == DMA_ENABLE_A::DISABLE
43    }
44}
45#[doc = "Field `receive_dma` writer - Enable signal of receive DMA interface"]
46pub type RECEIVE_DMA_W<'a, REG> = crate::BitWriter<'a, REG, DMA_ENABLE_A>;
47impl<'a, REG> RECEIVE_DMA_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Enable DMA interface"]
52    #[inline(always)]
53    pub fn enable(self) -> &'a mut crate::W<REG> {
54        self.variant(DMA_ENABLE_A::ENABLE)
55    }
56    #[doc = "Disable DMA interface"]
57    #[inline(always)]
58    pub fn disable(self) -> &'a mut crate::W<REG> {
59        self.variant(DMA_ENABLE_A::DISABLE)
60    }
61}
62#[doc = "Field `transmit_clear` writer - Clears transmit FIFO overflow and underflow flags"]
63pub use RECEIVE_CLEAR_W as TRANSMIT_CLEAR_W;
64#[doc = "Clears receive FIFO overflow and underflow flags\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum FLAG_CLEAR_AW {
67    #[doc = "1: Write 1 to clear fifo flags"]
68    CLEAR = 1,
69}
70impl From<FLAG_CLEAR_AW> for bool {
71    #[inline(always)]
72    fn from(variant: FLAG_CLEAR_AW) -> Self {
73        variant as u8 != 0
74    }
75}
76#[doc = "Field `receive_clear` writer - Clears receive FIFO overflow and underflow flags"]
77pub type RECEIVE_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG, FLAG_CLEAR_AW>;
78impl<'a, REG> RECEIVE_CLEAR_W<'a, REG>
79where
80    REG: crate::Writable + crate::RegisterSpec,
81{
82    #[doc = "Write 1 to clear fifo flags"]
83    #[inline(always)]
84    pub fn clear(self) -> &'a mut crate::W<REG> {
85        self.variant(FLAG_CLEAR_AW::CLEAR)
86    }
87}
88#[doc = "Field `transmit_overflow` reader - Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`."]
89pub use RECEIVE_OVERFLOW_R as TRANSMIT_OVERFLOW_R;
90#[doc = "Field `transmit_underflow` reader - Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`."]
91pub use RECEIVE_UNDERFLOW_R as TRANSMIT_UNDERFLOW_R;
92#[doc = "Field `receive_overflow` reader - Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`."]
93pub type RECEIVE_OVERFLOW_R = crate::BitReader<HAS_OVERFLOW_A>;
94#[doc = "Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`.\n\nValue on reset: 0"]
95#[derive(Clone, Copy, Debug, PartialEq, Eq)]
96pub enum HAS_OVERFLOW_A {
97    #[doc = "0: No FIFO buffer overflow"]
98    NOT_OVERFLOW = 0,
99    #[doc = "1: Has FIFO buffer overflow"]
100    OVERFLOW = 1,
101}
102impl From<HAS_OVERFLOW_A> for bool {
103    #[inline(always)]
104    fn from(variant: HAS_OVERFLOW_A) -> Self {
105        variant as u8 != 0
106    }
107}
108impl RECEIVE_OVERFLOW_R {
109    #[doc = "Get enumerated values variant"]
110    #[inline(always)]
111    pub const fn variant(&self) -> HAS_OVERFLOW_A {
112        match self.bits {
113            false => HAS_OVERFLOW_A::NOT_OVERFLOW,
114            true => HAS_OVERFLOW_A::OVERFLOW,
115        }
116    }
117    #[doc = "No FIFO buffer overflow"]
118    #[inline(always)]
119    pub fn is_not_overflow(&self) -> bool {
120        *self == HAS_OVERFLOW_A::NOT_OVERFLOW
121    }
122    #[doc = "Has FIFO buffer overflow"]
123    #[inline(always)]
124    pub fn is_overflow(&self) -> bool {
125        *self == HAS_OVERFLOW_A::OVERFLOW
126    }
127}
128#[doc = "Field `receive_underflow` reader - Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`."]
129pub type RECEIVE_UNDERFLOW_R = crate::BitReader<HAS_UNDERFLOW_A>;
130#[doc = "Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`.\n\nValue on reset: 0"]
131#[derive(Clone, Copy, Debug, PartialEq, Eq)]
132pub enum HAS_UNDERFLOW_A {
133    #[doc = "0: No FIFO buffer underflow"]
134    NOT_UNDERFLOW = 0,
135    #[doc = "1: Has FIFO buffer underflow"]
136    UNDERFLOW = 1,
137}
138impl From<HAS_UNDERFLOW_A> for bool {
139    #[inline(always)]
140    fn from(variant: HAS_UNDERFLOW_A) -> Self {
141        variant as u8 != 0
142    }
143}
144impl RECEIVE_UNDERFLOW_R {
145    #[doc = "Get enumerated values variant"]
146    #[inline(always)]
147    pub const fn variant(&self) -> HAS_UNDERFLOW_A {
148        match self.bits {
149            false => HAS_UNDERFLOW_A::NOT_UNDERFLOW,
150            true => HAS_UNDERFLOW_A::UNDERFLOW,
151        }
152    }
153    #[doc = "No FIFO buffer underflow"]
154    #[inline(always)]
155    pub fn is_not_underflow(&self) -> bool {
156        *self == HAS_UNDERFLOW_A::NOT_UNDERFLOW
157    }
158    #[doc = "Has FIFO buffer underflow"]
159    #[inline(always)]
160    pub fn is_underflow(&self) -> bool {
161        *self == HAS_UNDERFLOW_A::UNDERFLOW
162    }
163}
164#[doc = "Field `merge_left_right` reader - "]
165pub type MERGE_LEFT_RIGHT_R = crate::BitReader;
166#[doc = "Field `merge_left_right` writer - "]
167pub type MERGE_LEFT_RIGHT_W<'a, REG> = crate::BitWriter<'a, REG>;
168#[doc = "Field `swap_left_right` reader - "]
169pub type SWAP_LEFT_RIGHT_R = crate::BitReader;
170#[doc = "Field `swap_left_right` writer - "]
171pub type SWAP_LEFT_RIGHT_W<'a, REG> = crate::BitWriter<'a, REG>;
172#[doc = "Field `left_justified` reader - "]
173pub type LEFT_JUSTIFIED_R = crate::BitReader;
174#[doc = "Field `left_justified` writer - "]
175pub type LEFT_JUSTIFIED_W<'a, REG> = crate::BitWriter<'a, REG>;
176impl R {
177    #[doc = "Bit 0 - Enable signal of transmit DMA interface"]
178    #[inline(always)]
179    pub fn transmit_dma(&self) -> TRANSMIT_DMA_R {
180        TRANSMIT_DMA_R::new((self.bits & 1) != 0)
181    }
182    #[doc = "Bit 1 - Enable signal of receive DMA interface"]
183    #[inline(always)]
184    pub fn receive_dma(&self) -> RECEIVE_DMA_R {
185        RECEIVE_DMA_R::new(((self.bits >> 1) & 1) != 0)
186    }
187    #[doc = "Bit 4 - Transmit FIFO overflow flag\n\n Can be cleared using `transmit_clear`."]
188    #[inline(always)]
189    pub fn transmit_overflow(&self) -> TRANSMIT_OVERFLOW_R {
190        TRANSMIT_OVERFLOW_R::new(((self.bits >> 4) & 1) != 0)
191    }
192    #[doc = "Bit 5 - Transmit FIFO underflow flag\n\n Can be cleared using `transmit_clear`."]
193    #[inline(always)]
194    pub fn transmit_underflow(&self) -> TRANSMIT_UNDERFLOW_R {
195        TRANSMIT_UNDERFLOW_R::new(((self.bits >> 5) & 1) != 0)
196    }
197    #[doc = "Bit 6 - Receive FIFO overflow flag\n\n Can be cleared using `receive_clear`."]
198    #[inline(always)]
199    pub fn receive_overflow(&self) -> RECEIVE_OVERFLOW_R {
200        RECEIVE_OVERFLOW_R::new(((self.bits >> 6) & 1) != 0)
201    }
202    #[doc = "Bit 7 - Receive FIFO underflow flag\n\n Can be cleared using `receive_clear`."]
203    #[inline(always)]
204    pub fn receive_underflow(&self) -> RECEIVE_UNDERFLOW_R {
205        RECEIVE_UNDERFLOW_R::new(((self.bits >> 7) & 1) != 0)
206    }
207    #[doc = "Bit 8"]
208    #[inline(always)]
209    pub fn merge_left_right(&self) -> MERGE_LEFT_RIGHT_R {
210        MERGE_LEFT_RIGHT_R::new(((self.bits >> 8) & 1) != 0)
211    }
212    #[doc = "Bit 9"]
213    #[inline(always)]
214    pub fn swap_left_right(&self) -> SWAP_LEFT_RIGHT_R {
215        SWAP_LEFT_RIGHT_R::new(((self.bits >> 9) & 1) != 0)
216    }
217    #[doc = "Bit 10"]
218    #[inline(always)]
219    pub fn left_justified(&self) -> LEFT_JUSTIFIED_R {
220        LEFT_JUSTIFIED_R::new(((self.bits >> 10) & 1) != 0)
221    }
222}
223impl W {
224    #[doc = "Bit 0 - Enable signal of transmit DMA interface"]
225    #[inline(always)]
226    #[must_use]
227    pub fn transmit_dma(&mut self) -> TRANSMIT_DMA_W<FIFO_CONFIG_0_SPEC> {
228        TRANSMIT_DMA_W::new(self, 0)
229    }
230    #[doc = "Bit 1 - Enable signal of receive DMA interface"]
231    #[inline(always)]
232    #[must_use]
233    pub fn receive_dma(&mut self) -> RECEIVE_DMA_W<FIFO_CONFIG_0_SPEC> {
234        RECEIVE_DMA_W::new(self, 1)
235    }
236    #[doc = "Bit 2 - Clears transmit FIFO overflow and underflow flags"]
237    #[inline(always)]
238    #[must_use]
239    pub fn transmit_clear(&mut self) -> TRANSMIT_CLEAR_W<FIFO_CONFIG_0_SPEC> {
240        TRANSMIT_CLEAR_W::new(self, 2)
241    }
242    #[doc = "Bit 3 - Clears receive FIFO overflow and underflow flags"]
243    #[inline(always)]
244    #[must_use]
245    pub fn receive_clear(&mut self) -> RECEIVE_CLEAR_W<FIFO_CONFIG_0_SPEC> {
246        RECEIVE_CLEAR_W::new(self, 3)
247    }
248    #[doc = "Bit 8"]
249    #[inline(always)]
250    #[must_use]
251    pub fn merge_left_right(&mut self) -> MERGE_LEFT_RIGHT_W<FIFO_CONFIG_0_SPEC> {
252        MERGE_LEFT_RIGHT_W::new(self, 8)
253    }
254    #[doc = "Bit 9"]
255    #[inline(always)]
256    #[must_use]
257    pub fn swap_left_right(&mut self) -> SWAP_LEFT_RIGHT_W<FIFO_CONFIG_0_SPEC> {
258        SWAP_LEFT_RIGHT_W::new(self, 9)
259    }
260    #[doc = "Bit 10"]
261    #[inline(always)]
262    #[must_use]
263    pub fn left_justified(&mut self) -> LEFT_JUSTIFIED_W<FIFO_CONFIG_0_SPEC> {
264        LEFT_JUSTIFIED_W::new(self, 10)
265    }
266    #[doc = r" Writes raw bits to the register."]
267    #[doc = r""]
268    #[doc = r" # Safety"]
269    #[doc = r""]
270    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
271    #[inline(always)]
272    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
273        self.bits = bits;
274        self
275    }
276}
277#[doc = "FIFO configuration register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_config_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_config_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
278pub struct FIFO_CONFIG_0_SPEC;
279impl crate::RegisterSpec for FIFO_CONFIG_0_SPEC {
280    type Ux = u32;
281}
282#[doc = "`read()` method returns [`fifo_config_0::R`](R) reader structure"]
283impl crate::Readable for FIFO_CONFIG_0_SPEC {}
284#[doc = "`write(|w| ..)` method takes [`fifo_config_0::W`](W) writer structure"]
285impl crate::Writable for FIFO_CONFIG_0_SPEC {
286    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
287    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
288}
289#[doc = "`reset()` method sets fifo_config_0 to value 0"]
290impl crate::Resettable for FIFO_CONFIG_0_SPEC {
291    const RESET_VALUE: Self::Ux = 0;
292}
bl61x_pac/i2s/fifo_config_0.rs

bl61x_pac/i2s/
fifo_config_0.rs
