bl61x_pac/i2c/
bus_busy.rs

1#[doc = "Register `bus_busy` reader"]
2pub type R = crate::R<BUS_BUSY_SPEC>;
3#[doc = "Register `bus_busy` writer"]
4pub type W = crate::W<BUS_BUSY_SPEC>;
5#[doc = "Field `busy` reader - Indicator to I2C bus busy signal"]
6pub type BUSY_R = crate::BitReader<BUSY_A>;
7#[doc = "Indicator to I2C bus busy signal\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum BUSY_A {
10    #[doc = "1: Bus is busy"]
11    BUSY = 1,
12    #[doc = "0: Bus is not busy"]
13    IDLE = 0,
14}
15impl From<BUSY_A> for bool {
16    #[inline(always)]
17    fn from(variant: BUSY_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl BUSY_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> BUSY_A {
25        match self.bits {
26            true => BUSY_A::BUSY,
27            false => BUSY_A::IDLE,
28        }
29    }
30    #[doc = "Bus is busy"]
31    #[inline(always)]
32    pub fn is_busy(&self) -> bool {
33        *self == BUSY_A::BUSY
34    }
35    #[doc = "Bus is not busy"]
36    #[inline(always)]
37    pub fn is_idle(&self) -> bool {
38        *self == BUSY_A::IDLE
39    }
40}
41#[doc = "Force clear I2C bus busy state\n\n Not for normal use; only use when I2C bus hangs\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum FORCE_CLEAR_AW {
44    #[doc = "1: Write 1 to force clear busy flag"]
45    CLEAR = 1,
46}
47impl From<FORCE_CLEAR_AW> for bool {
48    #[inline(always)]
49    fn from(variant: FORCE_CLEAR_AW) -> Self {
50        variant as u8 != 0
51    }
52}
53#[doc = "Field `force_clear` writer - Force clear I2C bus busy state\n\n Not for normal use; only use when I2C bus hangs"]
54pub type FORCE_CLEAR_W<'a, REG> = crate::BitWriter<'a, REG, FORCE_CLEAR_AW>;
55impl<'a, REG> FORCE_CLEAR_W<'a, REG>
56where
57    REG: crate::Writable + crate::RegisterSpec,
58{
59    #[doc = "Write 1 to force clear busy flag"]
60    #[inline(always)]
61    pub fn clear(self) -> &'a mut crate::W<REG> {
62        self.variant(FORCE_CLEAR_AW::CLEAR)
63    }
64}
65impl R {
66    #[doc = "Bit 0 - Indicator to I2C bus busy signal"]
67    #[inline(always)]
68    pub fn busy(&self) -> BUSY_R {
69        BUSY_R::new((self.bits & 1) != 0)
70    }
71}
72impl W {
73    #[doc = "Bit 1 - Force clear I2C bus busy state\n\n Not for normal use; only use when I2C bus hangs"]
74    #[inline(always)]
75    #[must_use]
76    pub fn force_clear(&mut self) -> FORCE_CLEAR_W<BUS_BUSY_SPEC> {
77        FORCE_CLEAR_W::new(self, 1)
78    }
79    #[doc = r" Writes raw bits to the register."]
80    #[doc = r""]
81    #[doc = r" # Safety"]
82    #[doc = r""]
83    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
84    #[inline(always)]
85    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
86        self.bits = bits;
87        self
88    }
89}
90#[doc = "Bus busy state indicator\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`bus_busy::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`bus_busy::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
91pub struct BUS_BUSY_SPEC;
92impl crate::RegisterSpec for BUS_BUSY_SPEC {
93    type Ux = u32;
94}
95#[doc = "`read()` method returns [`bus_busy::R`](R) reader structure"]
96impl crate::Readable for BUS_BUSY_SPEC {}
97#[doc = "`write(|w| ..)` method takes [`bus_busy::W`](W) writer structure"]
98impl crate::Writable for BUS_BUSY_SPEC {
99    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
100    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
101}
102#[doc = "`reset()` method sets bus_busy to value 0"]
103impl crate::Resettable for BUS_BUSY_SPEC {
104    const RESET_VALUE: Self::Ux = 0;
105}
bl61x_pac/i2c/bus_busy.rs

bl61x_pac/i2c/
bus_busy.rs
