1#[doc = "Register `control` reader"]
2pub type R = crate::R<CONTROL_SPEC>;
3#[doc = "Register `control` writer"]
4pub type W = crate::W<CONTROL_SPEC>;
5#[doc = "Field `rtc_ctl` reader - "]
6pub type RTC_CTL_R = crate::FieldReader;
7#[doc = "Field `rtc_ctl` writer - "]
8pub type RTC_CTL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `rtc_dly_option` reader - "]
10pub type RTC_DLY_OPTION_R = crate::BitReader;
11#[doc = "Field `rtc_dly_option` writer - "]
12pub type RTC_DLY_OPTION_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `hbn_mode` reader - "]
14pub type HBN_MODE_R = crate::BitReader;
15#[doc = "Field `hbn_mode` writer - "]
16pub type HBN_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `trap_mode` reader - "]
18pub type TRAP_MODE_R = crate::BitReader;
19#[doc = "Field `trap_mode` writer - "]
20pub type TRAP_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `pwrdn_hbn_core` reader - "]
22pub type PWRDN_HBN_CORE_R = crate::BitReader;
23#[doc = "Field `pwrdn_hbn_core` writer - "]
24pub type PWRDN_HBN_CORE_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `pwrdn_hbn_rtc` reader - "]
26pub type PWRDN_HBN_RTC_R = crate::BitReader;
27#[doc = "Field `pwrdn_hbn_rtc` writer - "]
28pub type PWRDN_HBN_RTC_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `sw_rst` reader - "]
30pub type SW_RST_R = crate::BitReader;
31#[doc = "Field `sw_rst` writer - "]
32pub type SW_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `hbn_dis_pwr_off_ldo11` reader - "]
34pub type HBN_DIS_PWR_OFF_LDO11_R = crate::BitReader;
35#[doc = "Field `hbn_dis_pwr_off_ldo11` writer - "]
36pub type HBN_DIS_PWR_OFF_LDO11_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `hbn_dis_pwr_off_ldo11_rt` reader - "]
38pub type HBN_DIS_PWR_OFF_LDO11_RT_R = crate::BitReader;
39#[doc = "Field `hbn_dis_pwr_off_ldo11_rt` writer - "]
40pub type HBN_DIS_PWR_OFF_LDO11_RT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `hbn_ldo11_rt_vout_sel` reader - "]
42pub type HBN_LDO11_RT_VOUT_SEL_R = crate::FieldReader;
43#[doc = "Field `hbn_ldo11_rt_vout_sel` writer - "]
44pub type HBN_LDO11_RT_VOUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
45#[doc = "Field `hbn_ldo11_aon_vout_sel` reader - "]
46pub type HBN_LDO11_AON_VOUT_SEL_R = crate::FieldReader;
47#[doc = "Field `hbn_ldo11_aon_vout_sel` writer - "]
48pub type HBN_LDO11_AON_VOUT_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
49#[doc = "Field `pu_dcdc18_aon` reader - "]
50pub type PU_DCDC18_AON_R = crate::BitReader;
51#[doc = "Field `pu_dcdc18_aon` writer - "]
52pub type PU_DCDC18_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `pwr_on_option` reader - "]
54pub type PWR_ON_OPTION_R = crate::BitReader;
55#[doc = "Field `pwr_on_option` writer - "]
56pub type PWR_ON_OPTION_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `sram_slp_option` reader - "]
58pub type SRAM_SLP_OPTION_R = crate::BitReader;
59#[doc = "Field `sram_slp_option` writer - "]
60pub type SRAM_SLP_OPTION_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `sram_slp` reader - "]
62pub type SRAM_SLP_R = crate::BitReader;
63#[doc = "Field `sram_slp` writer - "]
64pub type SRAM_SLP_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `hbn_state` reader - "]
66pub type HBN_STATE_R = crate::FieldReader;
67#[doc = "Field `hbn_state` writer - "]
68pub type HBN_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
69impl R {
70 #[doc = "Bits 0:3"]
71 #[inline(always)]
72 pub fn rtc_ctl(&self) -> RTC_CTL_R {
73 RTC_CTL_R::new((self.bits & 0x0f) as u8)
74 }
75 #[doc = "Bit 4"]
76 #[inline(always)]
77 pub fn rtc_dly_option(&self) -> RTC_DLY_OPTION_R {
78 RTC_DLY_OPTION_R::new(((self.bits >> 4) & 1) != 0)
79 }
80 #[doc = "Bit 7"]
81 #[inline(always)]
82 pub fn hbn_mode(&self) -> HBN_MODE_R {
83 HBN_MODE_R::new(((self.bits >> 7) & 1) != 0)
84 }
85 #[doc = "Bit 8"]
86 #[inline(always)]
87 pub fn trap_mode(&self) -> TRAP_MODE_R {
88 TRAP_MODE_R::new(((self.bits >> 8) & 1) != 0)
89 }
90 #[doc = "Bit 9"]
91 #[inline(always)]
92 pub fn pwrdn_hbn_core(&self) -> PWRDN_HBN_CORE_R {
93 PWRDN_HBN_CORE_R::new(((self.bits >> 9) & 1) != 0)
94 }
95 #[doc = "Bit 11"]
96 #[inline(always)]
97 pub fn pwrdn_hbn_rtc(&self) -> PWRDN_HBN_RTC_R {
98 PWRDN_HBN_RTC_R::new(((self.bits >> 11) & 1) != 0)
99 }
100 #[doc = "Bit 12"]
101 #[inline(always)]
102 pub fn sw_rst(&self) -> SW_RST_R {
103 SW_RST_R::new(((self.bits >> 12) & 1) != 0)
104 }
105 #[doc = "Bit 13"]
106 #[inline(always)]
107 pub fn hbn_dis_pwr_off_ldo11(&self) -> HBN_DIS_PWR_OFF_LDO11_R {
108 HBN_DIS_PWR_OFF_LDO11_R::new(((self.bits >> 13) & 1) != 0)
109 }
110 #[doc = "Bit 14"]
111 #[inline(always)]
112 pub fn hbn_dis_pwr_off_ldo11_rt(&self) -> HBN_DIS_PWR_OFF_LDO11_RT_R {
113 HBN_DIS_PWR_OFF_LDO11_RT_R::new(((self.bits >> 14) & 1) != 0)
114 }
115 #[doc = "Bits 15:18"]
116 #[inline(always)]
117 pub fn hbn_ldo11_rt_vout_sel(&self) -> HBN_LDO11_RT_VOUT_SEL_R {
118 HBN_LDO11_RT_VOUT_SEL_R::new(((self.bits >> 15) & 0x0f) as u8)
119 }
120 #[doc = "Bits 19:22"]
121 #[inline(always)]
122 pub fn hbn_ldo11_aon_vout_sel(&self) -> HBN_LDO11_AON_VOUT_SEL_R {
123 HBN_LDO11_AON_VOUT_SEL_R::new(((self.bits >> 19) & 0x0f) as u8)
124 }
125 #[doc = "Bit 24"]
126 #[inline(always)]
127 pub fn pu_dcdc18_aon(&self) -> PU_DCDC18_AON_R {
128 PU_DCDC18_AON_R::new(((self.bits >> 24) & 1) != 0)
129 }
130 #[doc = "Bit 25"]
131 #[inline(always)]
132 pub fn pwr_on_option(&self) -> PWR_ON_OPTION_R {
133 PWR_ON_OPTION_R::new(((self.bits >> 25) & 1) != 0)
134 }
135 #[doc = "Bit 26"]
136 #[inline(always)]
137 pub fn sram_slp_option(&self) -> SRAM_SLP_OPTION_R {
138 SRAM_SLP_OPTION_R::new(((self.bits >> 26) & 1) != 0)
139 }
140 #[doc = "Bit 27"]
141 #[inline(always)]
142 pub fn sram_slp(&self) -> SRAM_SLP_R {
143 SRAM_SLP_R::new(((self.bits >> 27) & 1) != 0)
144 }
145 #[doc = "Bits 28:31"]
146 #[inline(always)]
147 pub fn hbn_state(&self) -> HBN_STATE_R {
148 HBN_STATE_R::new(((self.bits >> 28) & 0x0f) as u8)
149 }
150}
151impl W {
152 #[doc = "Bits 0:3"]
153 #[inline(always)]
154 #[must_use]
155 pub fn rtc_ctl(&mut self) -> RTC_CTL_W<CONTROL_SPEC> {
156 RTC_CTL_W::new(self, 0)
157 }
158 #[doc = "Bit 4"]
159 #[inline(always)]
160 #[must_use]
161 pub fn rtc_dly_option(&mut self) -> RTC_DLY_OPTION_W<CONTROL_SPEC> {
162 RTC_DLY_OPTION_W::new(self, 4)
163 }
164 #[doc = "Bit 7"]
165 #[inline(always)]
166 #[must_use]
167 pub fn hbn_mode(&mut self) -> HBN_MODE_W<CONTROL_SPEC> {
168 HBN_MODE_W::new(self, 7)
169 }
170 #[doc = "Bit 8"]
171 #[inline(always)]
172 #[must_use]
173 pub fn trap_mode(&mut self) -> TRAP_MODE_W<CONTROL_SPEC> {
174 TRAP_MODE_W::new(self, 8)
175 }
176 #[doc = "Bit 9"]
177 #[inline(always)]
178 #[must_use]
179 pub fn pwrdn_hbn_core(&mut self) -> PWRDN_HBN_CORE_W<CONTROL_SPEC> {
180 PWRDN_HBN_CORE_W::new(self, 9)
181 }
182 #[doc = "Bit 11"]
183 #[inline(always)]
184 #[must_use]
185 pub fn pwrdn_hbn_rtc(&mut self) -> PWRDN_HBN_RTC_W<CONTROL_SPEC> {
186 PWRDN_HBN_RTC_W::new(self, 11)
187 }
188 #[doc = "Bit 12"]
189 #[inline(always)]
190 #[must_use]
191 pub fn sw_rst(&mut self) -> SW_RST_W<CONTROL_SPEC> {
192 SW_RST_W::new(self, 12)
193 }
194 #[doc = "Bit 13"]
195 #[inline(always)]
196 #[must_use]
197 pub fn hbn_dis_pwr_off_ldo11(&mut self) -> HBN_DIS_PWR_OFF_LDO11_W<CONTROL_SPEC> {
198 HBN_DIS_PWR_OFF_LDO11_W::new(self, 13)
199 }
200 #[doc = "Bit 14"]
201 #[inline(always)]
202 #[must_use]
203 pub fn hbn_dis_pwr_off_ldo11_rt(&mut self) -> HBN_DIS_PWR_OFF_LDO11_RT_W<CONTROL_SPEC> {
204 HBN_DIS_PWR_OFF_LDO11_RT_W::new(self, 14)
205 }
206 #[doc = "Bits 15:18"]
207 #[inline(always)]
208 #[must_use]
209 pub fn hbn_ldo11_rt_vout_sel(&mut self) -> HBN_LDO11_RT_VOUT_SEL_W<CONTROL_SPEC> {
210 HBN_LDO11_RT_VOUT_SEL_W::new(self, 15)
211 }
212 #[doc = "Bits 19:22"]
213 #[inline(always)]
214 #[must_use]
215 pub fn hbn_ldo11_aon_vout_sel(&mut self) -> HBN_LDO11_AON_VOUT_SEL_W<CONTROL_SPEC> {
216 HBN_LDO11_AON_VOUT_SEL_W::new(self, 19)
217 }
218 #[doc = "Bit 24"]
219 #[inline(always)]
220 #[must_use]
221 pub fn pu_dcdc18_aon(&mut self) -> PU_DCDC18_AON_W<CONTROL_SPEC> {
222 PU_DCDC18_AON_W::new(self, 24)
223 }
224 #[doc = "Bit 25"]
225 #[inline(always)]
226 #[must_use]
227 pub fn pwr_on_option(&mut self) -> PWR_ON_OPTION_W<CONTROL_SPEC> {
228 PWR_ON_OPTION_W::new(self, 25)
229 }
230 #[doc = "Bit 26"]
231 #[inline(always)]
232 #[must_use]
233 pub fn sram_slp_option(&mut self) -> SRAM_SLP_OPTION_W<CONTROL_SPEC> {
234 SRAM_SLP_OPTION_W::new(self, 26)
235 }
236 #[doc = "Bit 27"]
237 #[inline(always)]
238 #[must_use]
239 pub fn sram_slp(&mut self) -> SRAM_SLP_W<CONTROL_SPEC> {
240 SRAM_SLP_W::new(self, 27)
241 }
242 #[doc = "Bits 28:31"]
243 #[inline(always)]
244 #[must_use]
245 pub fn hbn_state(&mut self) -> HBN_STATE_W<CONTROL_SPEC> {
246 HBN_STATE_W::new(self, 28)
247 }
248 #[doc = r" Writes raw bits to the register."]
249 #[doc = r""]
250 #[doc = r" # Safety"]
251 #[doc = r""]
252 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
253 #[inline(always)]
254 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
255 self.bits = bits;
256 self
257 }
258}
259#[doc = "Miscellaneous control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
260pub struct CONTROL_SPEC;
261impl crate::RegisterSpec for CONTROL_SPEC {
262 type Ux = u32;
263}
264#[doc = "`read()` method returns [`control::R`](R) reader structure"]
265impl crate::Readable for CONTROL_SPEC {}
266#[doc = "`write(|w| ..)` method takes [`control::W`](W) writer structure"]
267impl crate::Writable for CONTROL_SPEC {
268 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
269 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
270}
271#[doc = "`reset()` method sets control to value 0"]
272impl crate::Resettable for CONTROL_SPEC {
273 const RESET_VALUE: Self::Ux = 0;
274}