bl61x_pac/cci/
cci_ctl.rs

1#[doc = "Register `cci_ctl` reader"]
2pub type R = crate::R<CCI_CTL_SPEC>;
3#[doc = "Register `cci_ctl` writer"]
4pub type W = crate::W<CCI_CTL_SPEC>;
5#[doc = "Field `cci_write_flag` reader - "]
6pub type CCI_WRITE_FLAG_R = crate::BitReader;
7#[doc = "Field `cci_write_flag` writer - "]
8pub type CCI_WRITE_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `cci_read_flag` reader - "]
10pub type CCI_READ_FLAG_R = crate::BitReader;
11#[doc = "Field `cci_read_flag` writer - "]
12pub type CCI_READ_FLAG_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ahb_state` reader - "]
14pub type AHB_STATE_R = crate::FieldReader;
15#[doc = "Field `ahb_state` writer - "]
16pub type AHB_STATE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    #[doc = "Bit 0"]
19    #[inline(always)]
20    pub fn cci_write_flag(&self) -> CCI_WRITE_FLAG_R {
21        CCI_WRITE_FLAG_R::new((self.bits & 1) != 0)
22    }
23    #[doc = "Bit 1"]
24    #[inline(always)]
25    pub fn cci_read_flag(&self) -> CCI_READ_FLAG_R {
26        CCI_READ_FLAG_R::new(((self.bits >> 1) & 1) != 0)
27    }
28    #[doc = "Bits 2:3"]
29    #[inline(always)]
30    pub fn ahb_state(&self) -> AHB_STATE_R {
31        AHB_STATE_R::new(((self.bits >> 2) & 3) as u8)
32    }
33}
34impl W {
35    #[doc = "Bit 0"]
36    #[inline(always)]
37    #[must_use]
38    pub fn cci_write_flag(&mut self) -> CCI_WRITE_FLAG_W<CCI_CTL_SPEC> {
39        CCI_WRITE_FLAG_W::new(self, 0)
40    }
41    #[doc = "Bit 1"]
42    #[inline(always)]
43    #[must_use]
44    pub fn cci_read_flag(&mut self) -> CCI_READ_FLAG_W<CCI_CTL_SPEC> {
45        CCI_READ_FLAG_W::new(self, 1)
46    }
47    #[doc = "Bits 2:3"]
48    #[inline(always)]
49    #[must_use]
50    pub fn ahb_state(&mut self) -> AHB_STATE_W<CCI_CTL_SPEC> {
51        AHB_STATE_W::new(self, 2)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "cci_ctl.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cci_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cci_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct CCI_CTL_SPEC;
66impl crate::RegisterSpec for CCI_CTL_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`cci_ctl::R`](R) reader structure"]
70impl crate::Readable for CCI_CTL_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`cci_ctl::W`](W) writer structure"]
72impl crate::Writable for CCI_CTL_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75}
76#[doc = "`reset()` method sets cci_ctl to value 0"]
77impl crate::Resettable for CCI_CTL_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
bl61x_pac/cci/cci_ctl.rs

bl61x_pac/cci/
cci_ctl.rs
