bl61x_pac/cci/
audio_pll_cfg0.rs1#[doc = "Register `audio_pll_cfg0` reader"]
2pub type R = crate::R<AUDIO_PLL_CFG0_SPEC>;
3#[doc = "Register `audio_pll_cfg0` writer"]
4pub type W = crate::W<AUDIO_PLL_CFG0_SPEC>;
5#[doc = "Field `aupll_sdm_rstb` reader - "]
6pub type AUPLL_SDM_RSTB_R = crate::BitReader;
7#[doc = "Field `aupll_sdm_rstb` writer - "]
8pub type AUPLL_SDM_RSTB_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `aupll_postdiv_rstb` reader - "]
10pub type AUPLL_POSTDIV_RSTB_R = crate::BitReader;
11#[doc = "Field `aupll_postdiv_rstb` writer - "]
12pub type AUPLL_POSTDIV_RSTB_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `aupll_fbdv_rstb` reader - "]
14pub type AUPLL_FBDV_RSTB_R = crate::BitReader;
15#[doc = "Field `aupll_fbdv_rstb` writer - "]
16pub type AUPLL_FBDV_RSTB_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `aupll_refdiv_rstb` reader - "]
18pub type AUPLL_REFDIV_RSTB_R = crate::BitReader;
19#[doc = "Field `aupll_refdiv_rstb` writer - "]
20pub type AUPLL_REFDIV_RSTB_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `pu_aupll_postdiv` reader - "]
22pub type PU_AUPLL_POSTDIV_R = crate::BitReader;
23#[doc = "Field `pu_aupll_postdiv` writer - "]
24pub type PU_AUPLL_POSTDIV_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `pu_aupll_fbdv` reader - "]
26pub type PU_AUPLL_FBDV_R = crate::BitReader;
27#[doc = "Field `pu_aupll_fbdv` writer - "]
28pub type PU_AUPLL_FBDV_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `pu_aupll_clamp_op` reader - "]
30pub type PU_AUPLL_CLAMP_OP_R = crate::BitReader;
31#[doc = "Field `pu_aupll_clamp_op` writer - "]
32pub type PU_AUPLL_CLAMP_OP_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `pu_aupll_pfd` reader - "]
34pub type PU_AUPLL_PFD_R = crate::BitReader;
35#[doc = "Field `pu_aupll_pfd` writer - "]
36pub type PU_AUPLL_PFD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `pu_aupll_cp` reader - "]
38pub type PU_AUPLL_CP_R = crate::BitReader;
39#[doc = "Field `pu_aupll_cp` writer - "]
40pub type PU_AUPLL_CP_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `pu_aupll_sfreg` reader - "]
42pub type PU_AUPLL_SFREG_R = crate::BitReader;
43#[doc = "Field `pu_aupll_sfreg` writer - "]
44pub type PU_AUPLL_SFREG_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `pu_aupll` reader - "]
46pub type PU_AUPLL_R = crate::BitReader;
47#[doc = "Field `pu_aupll` writer - "]
48pub type PU_AUPLL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `pu_aupll_clktree` reader - "]
50pub type PU_AUPLL_CLKTREE_R = crate::BitReader;
51#[doc = "Field `pu_aupll_clktree` writer - "]
52pub type PU_AUPLL_CLKTREE_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bit 0"]
55 #[inline(always)]
56 pub fn aupll_sdm_rstb(&self) -> AUPLL_SDM_RSTB_R {
57 AUPLL_SDM_RSTB_R::new((self.bits & 1) != 0)
58 }
59 #[doc = "Bit 1"]
60 #[inline(always)]
61 pub fn aupll_postdiv_rstb(&self) -> AUPLL_POSTDIV_RSTB_R {
62 AUPLL_POSTDIV_RSTB_R::new(((self.bits >> 1) & 1) != 0)
63 }
64 #[doc = "Bit 2"]
65 #[inline(always)]
66 pub fn aupll_fbdv_rstb(&self) -> AUPLL_FBDV_RSTB_R {
67 AUPLL_FBDV_RSTB_R::new(((self.bits >> 2) & 1) != 0)
68 }
69 #[doc = "Bit 3"]
70 #[inline(always)]
71 pub fn aupll_refdiv_rstb(&self) -> AUPLL_REFDIV_RSTB_R {
72 AUPLL_REFDIV_RSTB_R::new(((self.bits >> 3) & 1) != 0)
73 }
74 #[doc = "Bit 4"]
75 #[inline(always)]
76 pub fn pu_aupll_postdiv(&self) -> PU_AUPLL_POSTDIV_R {
77 PU_AUPLL_POSTDIV_R::new(((self.bits >> 4) & 1) != 0)
78 }
79 #[doc = "Bit 5"]
80 #[inline(always)]
81 pub fn pu_aupll_fbdv(&self) -> PU_AUPLL_FBDV_R {
82 PU_AUPLL_FBDV_R::new(((self.bits >> 5) & 1) != 0)
83 }
84 #[doc = "Bit 6"]
85 #[inline(always)]
86 pub fn pu_aupll_clamp_op(&self) -> PU_AUPLL_CLAMP_OP_R {
87 PU_AUPLL_CLAMP_OP_R::new(((self.bits >> 6) & 1) != 0)
88 }
89 #[doc = "Bit 7"]
90 #[inline(always)]
91 pub fn pu_aupll_pfd(&self) -> PU_AUPLL_PFD_R {
92 PU_AUPLL_PFD_R::new(((self.bits >> 7) & 1) != 0)
93 }
94 #[doc = "Bit 8"]
95 #[inline(always)]
96 pub fn pu_aupll_cp(&self) -> PU_AUPLL_CP_R {
97 PU_AUPLL_CP_R::new(((self.bits >> 8) & 1) != 0)
98 }
99 #[doc = "Bit 9"]
100 #[inline(always)]
101 pub fn pu_aupll_sfreg(&self) -> PU_AUPLL_SFREG_R {
102 PU_AUPLL_SFREG_R::new(((self.bits >> 9) & 1) != 0)
103 }
104 #[doc = "Bit 10"]
105 #[inline(always)]
106 pub fn pu_aupll(&self) -> PU_AUPLL_R {
107 PU_AUPLL_R::new(((self.bits >> 10) & 1) != 0)
108 }
109 #[doc = "Bit 11"]
110 #[inline(always)]
111 pub fn pu_aupll_clktree(&self) -> PU_AUPLL_CLKTREE_R {
112 PU_AUPLL_CLKTREE_R::new(((self.bits >> 11) & 1) != 0)
113 }
114}
115impl W {
116 #[doc = "Bit 0"]
117 #[inline(always)]
118 #[must_use]
119 pub fn aupll_sdm_rstb(&mut self) -> AUPLL_SDM_RSTB_W<AUDIO_PLL_CFG0_SPEC> {
120 AUPLL_SDM_RSTB_W::new(self, 0)
121 }
122 #[doc = "Bit 1"]
123 #[inline(always)]
124 #[must_use]
125 pub fn aupll_postdiv_rstb(&mut self) -> AUPLL_POSTDIV_RSTB_W<AUDIO_PLL_CFG0_SPEC> {
126 AUPLL_POSTDIV_RSTB_W::new(self, 1)
127 }
128 #[doc = "Bit 2"]
129 #[inline(always)]
130 #[must_use]
131 pub fn aupll_fbdv_rstb(&mut self) -> AUPLL_FBDV_RSTB_W<AUDIO_PLL_CFG0_SPEC> {
132 AUPLL_FBDV_RSTB_W::new(self, 2)
133 }
134 #[doc = "Bit 3"]
135 #[inline(always)]
136 #[must_use]
137 pub fn aupll_refdiv_rstb(&mut self) -> AUPLL_REFDIV_RSTB_W<AUDIO_PLL_CFG0_SPEC> {
138 AUPLL_REFDIV_RSTB_W::new(self, 3)
139 }
140 #[doc = "Bit 4"]
141 #[inline(always)]
142 #[must_use]
143 pub fn pu_aupll_postdiv(&mut self) -> PU_AUPLL_POSTDIV_W<AUDIO_PLL_CFG0_SPEC> {
144 PU_AUPLL_POSTDIV_W::new(self, 4)
145 }
146 #[doc = "Bit 5"]
147 #[inline(always)]
148 #[must_use]
149 pub fn pu_aupll_fbdv(&mut self) -> PU_AUPLL_FBDV_W<AUDIO_PLL_CFG0_SPEC> {
150 PU_AUPLL_FBDV_W::new(self, 5)
151 }
152 #[doc = "Bit 6"]
153 #[inline(always)]
154 #[must_use]
155 pub fn pu_aupll_clamp_op(&mut self) -> PU_AUPLL_CLAMP_OP_W<AUDIO_PLL_CFG0_SPEC> {
156 PU_AUPLL_CLAMP_OP_W::new(self, 6)
157 }
158 #[doc = "Bit 7"]
159 #[inline(always)]
160 #[must_use]
161 pub fn pu_aupll_pfd(&mut self) -> PU_AUPLL_PFD_W<AUDIO_PLL_CFG0_SPEC> {
162 PU_AUPLL_PFD_W::new(self, 7)
163 }
164 #[doc = "Bit 8"]
165 #[inline(always)]
166 #[must_use]
167 pub fn pu_aupll_cp(&mut self) -> PU_AUPLL_CP_W<AUDIO_PLL_CFG0_SPEC> {
168 PU_AUPLL_CP_W::new(self, 8)
169 }
170 #[doc = "Bit 9"]
171 #[inline(always)]
172 #[must_use]
173 pub fn pu_aupll_sfreg(&mut self) -> PU_AUPLL_SFREG_W<AUDIO_PLL_CFG0_SPEC> {
174 PU_AUPLL_SFREG_W::new(self, 9)
175 }
176 #[doc = "Bit 10"]
177 #[inline(always)]
178 #[must_use]
179 pub fn pu_aupll(&mut self) -> PU_AUPLL_W<AUDIO_PLL_CFG0_SPEC> {
180 PU_AUPLL_W::new(self, 10)
181 }
182 #[doc = "Bit 11"]
183 #[inline(always)]
184 #[must_use]
185 pub fn pu_aupll_clktree(&mut self) -> PU_AUPLL_CLKTREE_W<AUDIO_PLL_CFG0_SPEC> {
186 PU_AUPLL_CLKTREE_W::new(self, 11)
187 }
188 #[doc = r" Writes raw bits to the register."]
189 #[doc = r""]
190 #[doc = r" # Safety"]
191 #[doc = r""]
192 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
193 #[inline(always)]
194 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195 self.bits = bits;
196 self
197 }
198}
199#[doc = "audio_pll_cfg0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_pll_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_pll_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
200pub struct AUDIO_PLL_CFG0_SPEC;
201impl crate::RegisterSpec for AUDIO_PLL_CFG0_SPEC {
202 type Ux = u32;
203}
204#[doc = "`read()` method returns [`audio_pll_cfg0::R`](R) reader structure"]
205impl crate::Readable for AUDIO_PLL_CFG0_SPEC {}
206#[doc = "`write(|w| ..)` method takes [`audio_pll_cfg0::W`](W) writer structure"]
207impl crate::Writable for AUDIO_PLL_CFG0_SPEC {
208 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
209 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
210}
211#[doc = "`reset()` method sets audio_pll_cfg0 to value 0"]
212impl crate::Resettable for AUDIO_PLL_CFG0_SPEC {
213 const RESET_VALUE: Self::Ux = 0;
214}