bl61x_pac/tzc_sec/
tzc_se_ctrl_0.rs

1#[doc = "Register `tzc_se_ctrl_0` reader"]
2pub type R = crate::R<TZC_SE_CTRL_0_SPEC>;
3#[doc = "Register `tzc_se_ctrl_0` writer"]
4pub type W = crate::W<TZC_SE_CTRL_0_SPEC>;
5#[doc = "Field `tzc_se_sha_tzsid_en` reader - TZSID enable for SHA in Secure Engine."]
6pub type TZC_SE_SHA_TZSID_EN_R = crate::FieldReader;
7#[doc = "Field `tzc_se_sha_tzsid_en` writer - TZSID enable for SHA in Secure Engine."]
8pub type TZC_SE_SHA_TZSID_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `tzc_se_aes_tzsid_en` reader - TZSID enable for AES in Secure Engine."]
10pub type TZC_SE_AES_TZSID_EN_R = crate::FieldReader;
11#[doc = "Field `tzc_se_aes_tzsid_en` writer - TZSID enable for AES in Secure Engine."]
12pub type TZC_SE_AES_TZSID_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `tzc_se_trng_tzsid_en` reader - TZSID enable for TRNG in Secure Engine."]
14pub type TZC_SE_TRNG_TZSID_EN_R = crate::FieldReader;
15#[doc = "Field `tzc_se_trng_tzsid_en` writer - TZSID enable for TRNG in Secure Engine."]
16pub type TZC_SE_TRNG_TZSID_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `tzc_se_pka_tzsid_en` reader - TZSID enable for PKA in Secure Engine."]
18pub type TZC_SE_PKA_TZSID_EN_R = crate::FieldReader;
19#[doc = "Field `tzc_se_pka_tzsid_en` writer - TZSID enable for PKA in Secure Engine."]
20pub type TZC_SE_PKA_TZSID_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `tzc_se_cdet_tzsid_en` reader - TZSID enable for code detection in Secure Engine."]
22pub type TZC_SE_CDET_TZSID_EN_R = crate::FieldReader;
23#[doc = "Field `tzc_se_cdet_tzsid_en` writer - TZSID enable for code detection in Secure Engine."]
24pub type TZC_SE_CDET_TZSID_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `tzc_se_gmac_tzsid_en` reader - TZSID enable for GMAC in Secure Engine."]
26pub type TZC_SE_GMAC_TZSID_EN_R = crate::FieldReader;
27#[doc = "Field `tzc_se_gmac_tzsid_en` writer - TZSID enable for GMAC in Secure Engine."]
28pub type TZC_SE_GMAC_TZSID_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
29#[doc = "Field `tzc_se_tzsid_crmd` reader - TZSID control for CRMD in Secure Engine."]
30pub type TZC_SE_TZSID_CRMD_R = crate::BitReader;
31#[doc = "Field `tzc_se_tzsid_crmd` writer - TZSID control for CRMD in Secure Engine."]
32pub type TZC_SE_TZSID_CRMD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `tzc_se_wdt_dly` reader - Watchdog timer delay in Secure Engine."]
34pub type TZC_SE_WDT_DLY_R = crate::FieldReader<u16>;
35#[doc = "Field `tzc_se_wdt_dly` writer - Watchdog timer delay in Secure Engine."]
36pub type TZC_SE_WDT_DLY_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
37impl R {
38    #[doc = "Bits 0:1 - TZSID enable for SHA in Secure Engine."]
39    #[inline(always)]
40    pub fn tzc_se_sha_tzsid_en(&self) -> TZC_SE_SHA_TZSID_EN_R {
41        TZC_SE_SHA_TZSID_EN_R::new((self.bits & 3) as u8)
42    }
43    #[doc = "Bits 2:3 - TZSID enable for AES in Secure Engine."]
44    #[inline(always)]
45    pub fn tzc_se_aes_tzsid_en(&self) -> TZC_SE_AES_TZSID_EN_R {
46        TZC_SE_AES_TZSID_EN_R::new(((self.bits >> 2) & 3) as u8)
47    }
48    #[doc = "Bits 4:5 - TZSID enable for TRNG in Secure Engine."]
49    #[inline(always)]
50    pub fn tzc_se_trng_tzsid_en(&self) -> TZC_SE_TRNG_TZSID_EN_R {
51        TZC_SE_TRNG_TZSID_EN_R::new(((self.bits >> 4) & 3) as u8)
52    }
53    #[doc = "Bits 6:7 - TZSID enable for PKA in Secure Engine."]
54    #[inline(always)]
55    pub fn tzc_se_pka_tzsid_en(&self) -> TZC_SE_PKA_TZSID_EN_R {
56        TZC_SE_PKA_TZSID_EN_R::new(((self.bits >> 6) & 3) as u8)
57    }
58    #[doc = "Bits 8:9 - TZSID enable for code detection in Secure Engine."]
59    #[inline(always)]
60    pub fn tzc_se_cdet_tzsid_en(&self) -> TZC_SE_CDET_TZSID_EN_R {
61        TZC_SE_CDET_TZSID_EN_R::new(((self.bits >> 8) & 3) as u8)
62    }
63    #[doc = "Bits 10:11 - TZSID enable for GMAC in Secure Engine."]
64    #[inline(always)]
65    pub fn tzc_se_gmac_tzsid_en(&self) -> TZC_SE_GMAC_TZSID_EN_R {
66        TZC_SE_GMAC_TZSID_EN_R::new(((self.bits >> 10) & 3) as u8)
67    }
68    #[doc = "Bit 12 - TZSID control for CRMD in Secure Engine."]
69    #[inline(always)]
70    pub fn tzc_se_tzsid_crmd(&self) -> TZC_SE_TZSID_CRMD_R {
71        TZC_SE_TZSID_CRMD_R::new(((self.bits >> 12) & 1) != 0)
72    }
73    #[doc = "Bits 16:31 - Watchdog timer delay in Secure Engine."]
74    #[inline(always)]
75    pub fn tzc_se_wdt_dly(&self) -> TZC_SE_WDT_DLY_R {
76        TZC_SE_WDT_DLY_R::new(((self.bits >> 16) & 0xffff) as u16)
77    }
78}
79impl W {
80    #[doc = "Bits 0:1 - TZSID enable for SHA in Secure Engine."]
81    #[inline(always)]
82    #[must_use]
83    pub fn tzc_se_sha_tzsid_en(&mut self) -> TZC_SE_SHA_TZSID_EN_W<TZC_SE_CTRL_0_SPEC> {
84        TZC_SE_SHA_TZSID_EN_W::new(self, 0)
85    }
86    #[doc = "Bits 2:3 - TZSID enable for AES in Secure Engine."]
87    #[inline(always)]
88    #[must_use]
89    pub fn tzc_se_aes_tzsid_en(&mut self) -> TZC_SE_AES_TZSID_EN_W<TZC_SE_CTRL_0_SPEC> {
90        TZC_SE_AES_TZSID_EN_W::new(self, 2)
91    }
92    #[doc = "Bits 4:5 - TZSID enable for TRNG in Secure Engine."]
93    #[inline(always)]
94    #[must_use]
95    pub fn tzc_se_trng_tzsid_en(&mut self) -> TZC_SE_TRNG_TZSID_EN_W<TZC_SE_CTRL_0_SPEC> {
96        TZC_SE_TRNG_TZSID_EN_W::new(self, 4)
97    }
98    #[doc = "Bits 6:7 - TZSID enable for PKA in Secure Engine."]
99    #[inline(always)]
100    #[must_use]
101    pub fn tzc_se_pka_tzsid_en(&mut self) -> TZC_SE_PKA_TZSID_EN_W<TZC_SE_CTRL_0_SPEC> {
102        TZC_SE_PKA_TZSID_EN_W::new(self, 6)
103    }
104    #[doc = "Bits 8:9 - TZSID enable for code detection in Secure Engine."]
105    #[inline(always)]
106    #[must_use]
107    pub fn tzc_se_cdet_tzsid_en(&mut self) -> TZC_SE_CDET_TZSID_EN_W<TZC_SE_CTRL_0_SPEC> {
108        TZC_SE_CDET_TZSID_EN_W::new(self, 8)
109    }
110    #[doc = "Bits 10:11 - TZSID enable for GMAC in Secure Engine."]
111    #[inline(always)]
112    #[must_use]
113    pub fn tzc_se_gmac_tzsid_en(&mut self) -> TZC_SE_GMAC_TZSID_EN_W<TZC_SE_CTRL_0_SPEC> {
114        TZC_SE_GMAC_TZSID_EN_W::new(self, 10)
115    }
116    #[doc = "Bit 12 - TZSID control for CRMD in Secure Engine."]
117    #[inline(always)]
118    #[must_use]
119    pub fn tzc_se_tzsid_crmd(&mut self) -> TZC_SE_TZSID_CRMD_W<TZC_SE_CTRL_0_SPEC> {
120        TZC_SE_TZSID_CRMD_W::new(self, 12)
121    }
122    #[doc = "Bits 16:31 - Watchdog timer delay in Secure Engine."]
123    #[inline(always)]
124    #[must_use]
125    pub fn tzc_se_wdt_dly(&mut self) -> TZC_SE_WDT_DLY_W<TZC_SE_CTRL_0_SPEC> {
126        TZC_SE_WDT_DLY_W::new(self, 16)
127    }
128    #[doc = r" Writes raw bits to the register."]
129    #[doc = r""]
130    #[doc = r" # Safety"]
131    #[doc = r""]
132    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
133    #[inline(always)]
134    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
135        self.bits = bits;
136        self
137    }
138}
139#[doc = "TrustZone Controller Secure Engine Control 0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`tzc_se_ctrl_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`tzc_se_ctrl_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
140pub struct TZC_SE_CTRL_0_SPEC;
141impl crate::RegisterSpec for TZC_SE_CTRL_0_SPEC {
142    type Ux = u32;
143}
144#[doc = "`read()` method returns [`tzc_se_ctrl_0::R`](R) reader structure"]
145impl crate::Readable for TZC_SE_CTRL_0_SPEC {}
146#[doc = "`write(|w| ..)` method takes [`tzc_se_ctrl_0::W`](W) writer structure"]
147impl crate::Writable for TZC_SE_CTRL_0_SPEC {
148    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150}
151#[doc = "`reset()` method sets tzc_se_ctrl_0 to value 0"]
152impl crate::Resettable for TZC_SE_CTRL_0_SPEC {
153    const RESET_VALUE: Self::Ux = 0;
154}
bl61x_pac/tzc_sec/tzc_se_ctrl_0.rs

bl61x_pac/tzc_sec/
tzc_se_ctrl_0.rs
