bl61x_pac/pds/
pds_ram1.rs

1#[doc = "Register `pds_ram1` reader"]
2pub type R = crate::R<PDS_RAM1_SPEC>;
3#[doc = "Register `pds_ram1` writer"]
4pub type W = crate::W<PDS_RAM1_SPEC>;
5#[doc = "Field `cr_pds_ram_clk_cnt` reader - "]
6pub type CR_PDS_RAM_CLK_CNT_R = crate::FieldReader;
7#[doc = "Field `cr_pds_ram_clk_cnt` writer - "]
8pub type CR_PDS_RAM_CLK_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `cr_pds_ram_clk2_cnt` reader - "]
10pub type CR_PDS_RAM_CLK2_CNT_R = crate::FieldReader;
11#[doc = "Field `cr_pds_ram_clk2_cnt` writer - "]
12pub type CR_PDS_RAM_CLK2_CNT_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `cr_pds_ctrl_np_ram_clk` reader - "]
14pub type CR_PDS_CTRL_NP_RAM_CLK_R = crate::BitReader;
15#[doc = "Field `cr_pds_ctrl_np_ram_clk` writer - "]
16pub type CR_PDS_CTRL_NP_RAM_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `cr_pds_ctrl_wb_ram_clk` reader - "]
18pub type CR_PDS_CTRL_WB_RAM_CLK_R = crate::BitReader;
19#[doc = "Field `cr_pds_ctrl_wb_ram_clk` writer - "]
20pub type CR_PDS_CTRL_WB_RAM_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `cr_pds_ctrl_usb_ram_clk` reader - "]
22pub type CR_PDS_CTRL_USB_RAM_CLK_R = crate::BitReader;
23#[doc = "Field `cr_pds_ctrl_usb_ram_clk` writer - "]
24pub type CR_PDS_CTRL_USB_RAM_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `cr_pds_ctrl_misc_ram_clk` reader - "]
26pub type CR_PDS_CTRL_MISC_RAM_CLK_R = crate::BitReader;
27#[doc = "Field `cr_pds_ctrl_misc_ram_clk` writer - "]
28pub type CR_PDS_CTRL_MISC_RAM_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `cr_pds_ctrl_ram_clk2` reader - "]
30pub type CR_PDS_CTRL_RAM_CLK2_R = crate::BitReader;
31#[doc = "Field `cr_pds_ctrl_ram_clk2` writer - "]
32pub type CR_PDS_CTRL_RAM_CLK2_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `cr_pds_ctrl_ram_clk` reader - "]
34pub type CR_PDS_CTRL_RAM_CLK_R = crate::BitReader;
35#[doc = "Field `cr_pds_ctrl_ram_clk` writer - "]
36pub type CR_PDS_CTRL_RAM_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38    #[doc = "Bits 8:13"]
39    #[inline(always)]
40    pub fn cr_pds_ram_clk_cnt(&self) -> CR_PDS_RAM_CLK_CNT_R {
41        CR_PDS_RAM_CLK_CNT_R::new(((self.bits >> 8) & 0x3f) as u8)
42    }
43    #[doc = "Bits 16:21"]
44    #[inline(always)]
45    pub fn cr_pds_ram_clk2_cnt(&self) -> CR_PDS_RAM_CLK2_CNT_R {
46        CR_PDS_RAM_CLK2_CNT_R::new(((self.bits >> 16) & 0x3f) as u8)
47    }
48    #[doc = "Bit 24"]
49    #[inline(always)]
50    pub fn cr_pds_ctrl_np_ram_clk(&self) -> CR_PDS_CTRL_NP_RAM_CLK_R {
51        CR_PDS_CTRL_NP_RAM_CLK_R::new(((self.bits >> 24) & 1) != 0)
52    }
53    #[doc = "Bit 26"]
54    #[inline(always)]
55    pub fn cr_pds_ctrl_wb_ram_clk(&self) -> CR_PDS_CTRL_WB_RAM_CLK_R {
56        CR_PDS_CTRL_WB_RAM_CLK_R::new(((self.bits >> 26) & 1) != 0)
57    }
58    #[doc = "Bit 27"]
59    #[inline(always)]
60    pub fn cr_pds_ctrl_usb_ram_clk(&self) -> CR_PDS_CTRL_USB_RAM_CLK_R {
61        CR_PDS_CTRL_USB_RAM_CLK_R::new(((self.bits >> 27) & 1) != 0)
62    }
63    #[doc = "Bit 28"]
64    #[inline(always)]
65    pub fn cr_pds_ctrl_misc_ram_clk(&self) -> CR_PDS_CTRL_MISC_RAM_CLK_R {
66        CR_PDS_CTRL_MISC_RAM_CLK_R::new(((self.bits >> 28) & 1) != 0)
67    }
68    #[doc = "Bit 30"]
69    #[inline(always)]
70    pub fn cr_pds_ctrl_ram_clk2(&self) -> CR_PDS_CTRL_RAM_CLK2_R {
71        CR_PDS_CTRL_RAM_CLK2_R::new(((self.bits >> 30) & 1) != 0)
72    }
73    #[doc = "Bit 31"]
74    #[inline(always)]
75    pub fn cr_pds_ctrl_ram_clk(&self) -> CR_PDS_CTRL_RAM_CLK_R {
76        CR_PDS_CTRL_RAM_CLK_R::new(((self.bits >> 31) & 1) != 0)
77    }
78}
79impl W {
80    #[doc = "Bits 8:13"]
81    #[inline(always)]
82    #[must_use]
83    pub fn cr_pds_ram_clk_cnt(&mut self) -> CR_PDS_RAM_CLK_CNT_W<PDS_RAM1_SPEC> {
84        CR_PDS_RAM_CLK_CNT_W::new(self, 8)
85    }
86    #[doc = "Bits 16:21"]
87    #[inline(always)]
88    #[must_use]
89    pub fn cr_pds_ram_clk2_cnt(&mut self) -> CR_PDS_RAM_CLK2_CNT_W<PDS_RAM1_SPEC> {
90        CR_PDS_RAM_CLK2_CNT_W::new(self, 16)
91    }
92    #[doc = "Bit 24"]
93    #[inline(always)]
94    #[must_use]
95    pub fn cr_pds_ctrl_np_ram_clk(&mut self) -> CR_PDS_CTRL_NP_RAM_CLK_W<PDS_RAM1_SPEC> {
96        CR_PDS_CTRL_NP_RAM_CLK_W::new(self, 24)
97    }
98    #[doc = "Bit 26"]
99    #[inline(always)]
100    #[must_use]
101    pub fn cr_pds_ctrl_wb_ram_clk(&mut self) -> CR_PDS_CTRL_WB_RAM_CLK_W<PDS_RAM1_SPEC> {
102        CR_PDS_CTRL_WB_RAM_CLK_W::new(self, 26)
103    }
104    #[doc = "Bit 27"]
105    #[inline(always)]
106    #[must_use]
107    pub fn cr_pds_ctrl_usb_ram_clk(&mut self) -> CR_PDS_CTRL_USB_RAM_CLK_W<PDS_RAM1_SPEC> {
108        CR_PDS_CTRL_USB_RAM_CLK_W::new(self, 27)
109    }
110    #[doc = "Bit 28"]
111    #[inline(always)]
112    #[must_use]
113    pub fn cr_pds_ctrl_misc_ram_clk(&mut self) -> CR_PDS_CTRL_MISC_RAM_CLK_W<PDS_RAM1_SPEC> {
114        CR_PDS_CTRL_MISC_RAM_CLK_W::new(self, 28)
115    }
116    #[doc = "Bit 30"]
117    #[inline(always)]
118    #[must_use]
119    pub fn cr_pds_ctrl_ram_clk2(&mut self) -> CR_PDS_CTRL_RAM_CLK2_W<PDS_RAM1_SPEC> {
120        CR_PDS_CTRL_RAM_CLK2_W::new(self, 30)
121    }
122    #[doc = "Bit 31"]
123    #[inline(always)]
124    #[must_use]
125    pub fn cr_pds_ctrl_ram_clk(&mut self) -> CR_PDS_CTRL_RAM_CLK_W<PDS_RAM1_SPEC> {
126        CR_PDS_CTRL_RAM_CLK_W::new(self, 31)
127    }
128    #[doc = r" Writes raw bits to the register."]
129    #[doc = r""]
130    #[doc = r" # Safety"]
131    #[doc = r""]
132    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
133    #[inline(always)]
134    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
135        self.bits = bits;
136        self
137    }
138}
139#[doc = "pds_ram1.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pds_ram1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pds_ram1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
140pub struct PDS_RAM1_SPEC;
141impl crate::RegisterSpec for PDS_RAM1_SPEC {
142    type Ux = u32;
143}
144#[doc = "`read()` method returns [`pds_ram1::R`](R) reader structure"]
145impl crate::Readable for PDS_RAM1_SPEC {}
146#[doc = "`write(|w| ..)` method takes [`pds_ram1::W`](W) writer structure"]
147impl crate::Writable for PDS_RAM1_SPEC {
148    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150}
151#[doc = "`reset()` method sets pds_ram1 to value 0"]
152impl crate::Resettable for PDS_RAM1_SPEC {
153    const RESET_VALUE: Self::Ux = 0;
154}
bl61x_pac/pds/pds_ram1.rs

bl61x_pac/pds/
pds_ram1.rs
