bl61x_pac/i2s/
base_clock.rs

1#[doc = "Register `base_clock` reader"]
2pub type R = crate::R<BASE_CLOCK_SPEC>;
3#[doc = "Register `base_clock` writer"]
4pub type W = crate::W<BASE_CLOCK_SPEC>;
5#[doc = "Field `divide_low` reader - Lower half of base clock dividing factor"]
6pub type DIVIDE_LOW_R = crate::FieldReader<u16>;
7#[doc = "Field `divide_low` writer - Lower half of base clock dividing factor"]
8pub type DIVIDE_LOW_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9#[doc = "Field `divide_high` reader - Higher half of base clock dividing factor"]
10pub type DIVIDE_HIGH_R = crate::FieldReader<u16>;
11#[doc = "Field `divide_high` writer - Higher half of base clock dividing factor"]
12pub type DIVIDE_HIGH_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
13impl R {
14    #[doc = "Bits 0:11 - Lower half of base clock dividing factor"]
15    #[inline(always)]
16    pub fn divide_low(&self) -> DIVIDE_LOW_R {
17        DIVIDE_LOW_R::new((self.bits & 0x0fff) as u16)
18    }
19    #[doc = "Bits 16:27 - Higher half of base clock dividing factor"]
20    #[inline(always)]
21    pub fn divide_high(&self) -> DIVIDE_HIGH_R {
22        DIVIDE_HIGH_R::new(((self.bits >> 16) & 0x0fff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:11 - Lower half of base clock dividing factor"]
27    #[inline(always)]
28    #[must_use]
29    pub fn divide_low(&mut self) -> DIVIDE_LOW_W<BASE_CLOCK_SPEC> {
30        DIVIDE_LOW_W::new(self, 0)
31    }
32    #[doc = "Bits 16:27 - Higher half of base clock dividing factor"]
33    #[inline(always)]
34    #[must_use]
35    pub fn divide_high(&mut self) -> DIVIDE_HIGH_W<BASE_CLOCK_SPEC> {
36        DIVIDE_HIGH_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Base clock divider\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`base_clock::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`base_clock::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct BASE_CLOCK_SPEC;
51impl crate::RegisterSpec for BASE_CLOCK_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`base_clock::R`](R) reader structure"]
55impl crate::Readable for BASE_CLOCK_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`base_clock::W`](W) writer structure"]
57impl crate::Writable for BASE_CLOCK_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets base_clock to value 0x0001_0001"]
62impl crate::Resettable for BASE_CLOCK_SPEC {
63    const RESET_VALUE: Self::Ux = 0x0001_0001;
64}