bl61x_pac/glb/
spi_config.rs

1#[doc = "Register `spi_config` reader"]
2pub type R = crate::R<SPI_CONFIG_SPEC>;
3#[doc = "Register `spi_config` writer"]
4pub type W = crate::W<SPI_CONFIG_SPEC>;
5#[doc = "Field `clock_divide` reader - Peripheral clock divide factor"]
6pub type CLOCK_DIVIDE_R = crate::FieldReader;
7#[doc = "Field `clock_divide` writer - Peripheral clock divide factor"]
8pub type CLOCK_DIVIDE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `clock_enable` reader - Peripheral level clock gate enable"]
10pub type CLOCK_ENABLE_R = crate::BitReader;
11#[doc = "Field `clock_enable` writer - Peripheral level clock gate enable"]
12pub type CLOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `clock_source` reader - Peripheral clock source register"]
14pub type CLOCK_SOURCE_R = crate::BitReader;
15#[doc = "Field `clock_source` writer - Peripheral clock source register"]
16pub type CLOCK_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `pin_swap` reader - Swap Serial Peripheral Interface pin signals"]
18pub type PIN_SWAP_R = crate::FieldReader;
19#[doc = "Field `pin_swap` writer - Swap Serial Peripheral Interface pin signals"]
20pub type PIN_SWAP_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21impl R {
22    #[doc = "Bits 0:4 - Peripheral clock divide factor"]
23    #[inline(always)]
24    pub fn clock_divide(&self) -> CLOCK_DIVIDE_R {
25        CLOCK_DIVIDE_R::new((self.bits & 0x1f) as u8)
26    }
27    #[doc = "Bit 8 - Peripheral level clock gate enable"]
28    #[inline(always)]
29    pub fn clock_enable(&self) -> CLOCK_ENABLE_R {
30        CLOCK_ENABLE_R::new(((self.bits >> 8) & 1) != 0)
31    }
32    #[doc = "Bit 9 - Peripheral clock source register"]
33    #[inline(always)]
34    pub fn clock_source(&self) -> CLOCK_SOURCE_R {
35        CLOCK_SOURCE_R::new(((self.bits >> 9) & 1) != 0)
36    }
37    #[doc = "Bits 16:19 - Swap Serial Peripheral Interface pin signals"]
38    #[inline(always)]
39    pub fn pin_swap(&self) -> PIN_SWAP_R {
40        PIN_SWAP_R::new(((self.bits >> 16) & 0x0f) as u8)
41    }
42}
43impl W {
44    #[doc = "Bits 0:4 - Peripheral clock divide factor"]
45    #[inline(always)]
46    #[must_use]
47    pub fn clock_divide(&mut self) -> CLOCK_DIVIDE_W<SPI_CONFIG_SPEC> {
48        CLOCK_DIVIDE_W::new(self, 0)
49    }
50    #[doc = "Bit 8 - Peripheral level clock gate enable"]
51    #[inline(always)]
52    #[must_use]
53    pub fn clock_enable(&mut self) -> CLOCK_ENABLE_W<SPI_CONFIG_SPEC> {
54        CLOCK_ENABLE_W::new(self, 8)
55    }
56    #[doc = "Bit 9 - Peripheral clock source register"]
57    #[inline(always)]
58    #[must_use]
59    pub fn clock_source(&mut self) -> CLOCK_SOURCE_W<SPI_CONFIG_SPEC> {
60        CLOCK_SOURCE_W::new(self, 9)
61    }
62    #[doc = "Bits 16:19 - Swap Serial Peripheral Interface pin signals"]
63    #[inline(always)]
64    #[must_use]
65    pub fn pin_swap(&mut self) -> PIN_SWAP_W<SPI_CONFIG_SPEC> {
66        PIN_SWAP_W::new(self, 16)
67    }
68    #[doc = r" Writes raw bits to the register."]
69    #[doc = r""]
70    #[doc = r" # Safety"]
71    #[doc = r""]
72    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
73    #[inline(always)]
74    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
75        self.bits = bits;
76        self
77    }
78}
79#[doc = "Serial Peripheral Interface configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct SPI_CONFIG_SPEC;
81impl crate::RegisterSpec for SPI_CONFIG_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`spi_config::R`](R) reader structure"]
85impl crate::Readable for SPI_CONFIG_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`spi_config::W`](W) writer structure"]
87impl crate::Writable for SPI_CONFIG_SPEC {
88    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
89    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
90}
91#[doc = "`reset()` method sets spi_config to value 0"]
92impl crate::Resettable for SPI_CONFIG_SPEC {
93    const RESET_VALUE: Self::Ux = 0;
94}
bl61x_pac/glb/spi_config.rs

bl61x_pac/glb/
spi_config.rs
