bl61x_pac/glb/
glb_parm_cfg0.rs1#[doc = "Register `glb_parm_cfg0` reader"]
2pub type R = crate::R<GLB_PARM_CFG0_SPEC>;
3#[doc = "Register `glb_parm_cfg0` writer"]
4pub type W = crate::W<GLB_PARM_CFG0_SPEC>;
5#[doc = "Field `uart_swap_set` reader - "]
6pub type UART_SWAP_SET_R = crate::FieldReader;
7#[doc = "Field `uart_swap_set` writer - "]
8pub type UART_SWAP_SET_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `swap_sflash_io_3_io_0` reader - "]
10pub type SWAP_SFLASH_IO_3_IO_0_R = crate::BitReader;
11#[doc = "Field `swap_sflash_io_3_io_0` writer - "]
12pub type SWAP_SFLASH_IO_3_IO_0_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `sel_embedded_sflash` reader - "]
14pub type SEL_EMBEDDED_SFLASH_R = crate::BitReader;
15#[doc = "Field `sel_embedded_sflash` writer - "]
16pub type SEL_EMBEDDED_SFLASH_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `swap_sflash_io_2_cs` reader - "]
18pub type SWAP_SFLASH_IO_2_CS_R = crate::BitReader;
19#[doc = "Field `swap_sflash_io_2_cs` writer - "]
20pub type SWAP_SFLASH_IO_2_CS_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `swap_sflash2_io_3_io_0` reader - "]
22pub type SWAP_SFLASH2_IO_3_IO_0_R = crate::BitReader;
23#[doc = "Field `swap_sflash2_io_3_io_0` writer - "]
24pub type SWAP_SFLASH2_IO_3_IO_0_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `reg_spi_0_master_mode` reader - "]
26pub type REG_SPI_0_MASTER_MODE_R = crate::BitReader;
27#[doc = "Field `reg_spi_0_master_mode` writer - "]
28pub type REG_SPI_0_MASTER_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `reg_spi_0_swap` reader - "]
30pub type REG_SPI_0_SWAP_R = crate::BitReader;
31#[doc = "Field `reg_spi_0_swap` writer - "]
32pub type REG_SPI_0_SWAP_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `ant_switch_sel` reader - "]
34pub type ANT_SWITCH_SEL_R = crate::BitReader;
35#[doc = "Field `ant_switch_sel` writer - "]
36pub type ANT_SWITCH_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `p3_cci_use_io_10_13` reader - "]
38pub type P3_CCI_USE_IO_10_13_R = crate::BitReader;
39#[doc = "Field `p3_cci_use_io_10_13` writer - "]
40pub type P3_CCI_USE_IO_10_13_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `audio_test_mode` reader - "]
42pub type AUDIO_TEST_MODE_R = crate::BitReader;
43#[doc = "Field `audio_test_mode` writer - "]
44pub type AUDIO_TEST_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `sel_rf_audio_test` reader - "]
46pub type SEL_RF_AUDIO_TEST_R = crate::FieldReader;
47#[doc = "Field `sel_rf_audio_test` writer - "]
48pub type SEL_RF_AUDIO_TEST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
49impl R {
50 #[doc = "Bits 2:5"]
51 #[inline(always)]
52 pub fn uart_swap_set(&self) -> UART_SWAP_SET_R {
53 UART_SWAP_SET_R::new(((self.bits >> 2) & 0x0f) as u8)
54 }
55 #[doc = "Bit 8"]
56 #[inline(always)]
57 pub fn swap_sflash_io_3_io_0(&self) -> SWAP_SFLASH_IO_3_IO_0_R {
58 SWAP_SFLASH_IO_3_IO_0_R::new(((self.bits >> 8) & 1) != 0)
59 }
60 #[doc = "Bit 9"]
61 #[inline(always)]
62 pub fn sel_embedded_sflash(&self) -> SEL_EMBEDDED_SFLASH_R {
63 SEL_EMBEDDED_SFLASH_R::new(((self.bits >> 9) & 1) != 0)
64 }
65 #[doc = "Bit 10"]
66 #[inline(always)]
67 pub fn swap_sflash_io_2_cs(&self) -> SWAP_SFLASH_IO_2_CS_R {
68 SWAP_SFLASH_IO_2_CS_R::new(((self.bits >> 10) & 1) != 0)
69 }
70 #[doc = "Bit 11"]
71 #[inline(always)]
72 pub fn swap_sflash2_io_3_io_0(&self) -> SWAP_SFLASH2_IO_3_IO_0_R {
73 SWAP_SFLASH2_IO_3_IO_0_R::new(((self.bits >> 11) & 1) != 0)
74 }
75 #[doc = "Bit 12"]
76 #[inline(always)]
77 pub fn reg_spi_0_master_mode(&self) -> REG_SPI_0_MASTER_MODE_R {
78 REG_SPI_0_MASTER_MODE_R::new(((self.bits >> 12) & 1) != 0)
79 }
80 #[doc = "Bit 13"]
81 #[inline(always)]
82 pub fn reg_spi_0_swap(&self) -> REG_SPI_0_SWAP_R {
83 REG_SPI_0_SWAP_R::new(((self.bits >> 13) & 1) != 0)
84 }
85 #[doc = "Bit 15"]
86 #[inline(always)]
87 pub fn ant_switch_sel(&self) -> ANT_SWITCH_SEL_R {
88 ANT_SWITCH_SEL_R::new(((self.bits >> 15) & 1) != 0)
89 }
90 #[doc = "Bit 19"]
91 #[inline(always)]
92 pub fn p3_cci_use_io_10_13(&self) -> P3_CCI_USE_IO_10_13_R {
93 P3_CCI_USE_IO_10_13_R::new(((self.bits >> 19) & 1) != 0)
94 }
95 #[doc = "Bit 29"]
96 #[inline(always)]
97 pub fn audio_test_mode(&self) -> AUDIO_TEST_MODE_R {
98 AUDIO_TEST_MODE_R::new(((self.bits >> 29) & 1) != 0)
99 }
100 #[doc = "Bits 30:31"]
101 #[inline(always)]
102 pub fn sel_rf_audio_test(&self) -> SEL_RF_AUDIO_TEST_R {
103 SEL_RF_AUDIO_TEST_R::new(((self.bits >> 30) & 3) as u8)
104 }
105}
106impl W {
107 #[doc = "Bits 2:5"]
108 #[inline(always)]
109 #[must_use]
110 pub fn uart_swap_set(&mut self) -> UART_SWAP_SET_W<GLB_PARM_CFG0_SPEC> {
111 UART_SWAP_SET_W::new(self, 2)
112 }
113 #[doc = "Bit 8"]
114 #[inline(always)]
115 #[must_use]
116 pub fn swap_sflash_io_3_io_0(&mut self) -> SWAP_SFLASH_IO_3_IO_0_W<GLB_PARM_CFG0_SPEC> {
117 SWAP_SFLASH_IO_3_IO_0_W::new(self, 8)
118 }
119 #[doc = "Bit 9"]
120 #[inline(always)]
121 #[must_use]
122 pub fn sel_embedded_sflash(&mut self) -> SEL_EMBEDDED_SFLASH_W<GLB_PARM_CFG0_SPEC> {
123 SEL_EMBEDDED_SFLASH_W::new(self, 9)
124 }
125 #[doc = "Bit 10"]
126 #[inline(always)]
127 #[must_use]
128 pub fn swap_sflash_io_2_cs(&mut self) -> SWAP_SFLASH_IO_2_CS_W<GLB_PARM_CFG0_SPEC> {
129 SWAP_SFLASH_IO_2_CS_W::new(self, 10)
130 }
131 #[doc = "Bit 11"]
132 #[inline(always)]
133 #[must_use]
134 pub fn swap_sflash2_io_3_io_0(&mut self) -> SWAP_SFLASH2_IO_3_IO_0_W<GLB_PARM_CFG0_SPEC> {
135 SWAP_SFLASH2_IO_3_IO_0_W::new(self, 11)
136 }
137 #[doc = "Bit 12"]
138 #[inline(always)]
139 #[must_use]
140 pub fn reg_spi_0_master_mode(&mut self) -> REG_SPI_0_MASTER_MODE_W<GLB_PARM_CFG0_SPEC> {
141 REG_SPI_0_MASTER_MODE_W::new(self, 12)
142 }
143 #[doc = "Bit 13"]
144 #[inline(always)]
145 #[must_use]
146 pub fn reg_spi_0_swap(&mut self) -> REG_SPI_0_SWAP_W<GLB_PARM_CFG0_SPEC> {
147 REG_SPI_0_SWAP_W::new(self, 13)
148 }
149 #[doc = "Bit 15"]
150 #[inline(always)]
151 #[must_use]
152 pub fn ant_switch_sel(&mut self) -> ANT_SWITCH_SEL_W<GLB_PARM_CFG0_SPEC> {
153 ANT_SWITCH_SEL_W::new(self, 15)
154 }
155 #[doc = "Bit 19"]
156 #[inline(always)]
157 #[must_use]
158 pub fn p3_cci_use_io_10_13(&mut self) -> P3_CCI_USE_IO_10_13_W<GLB_PARM_CFG0_SPEC> {
159 P3_CCI_USE_IO_10_13_W::new(self, 19)
160 }
161 #[doc = "Bit 29"]
162 #[inline(always)]
163 #[must_use]
164 pub fn audio_test_mode(&mut self) -> AUDIO_TEST_MODE_W<GLB_PARM_CFG0_SPEC> {
165 AUDIO_TEST_MODE_W::new(self, 29)
166 }
167 #[doc = "Bits 30:31"]
168 #[inline(always)]
169 #[must_use]
170 pub fn sel_rf_audio_test(&mut self) -> SEL_RF_AUDIO_TEST_W<GLB_PARM_CFG0_SPEC> {
171 SEL_RF_AUDIO_TEST_W::new(self, 30)
172 }
173 #[doc = r" Writes raw bits to the register."]
174 #[doc = r""]
175 #[doc = r" # Safety"]
176 #[doc = r""]
177 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180 self.bits = bits;
181 self
182 }
183}
184#[doc = "glb_parm_cfg0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`glb_parm_cfg0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`glb_parm_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
185pub struct GLB_PARM_CFG0_SPEC;
186impl crate::RegisterSpec for GLB_PARM_CFG0_SPEC {
187 type Ux = u32;
188}
189#[doc = "`read()` method returns [`glb_parm_cfg0::R`](R) reader structure"]
190impl crate::Readable for GLB_PARM_CFG0_SPEC {}
191#[doc = "`write(|w| ..)` method takes [`glb_parm_cfg0::W`](W) writer structure"]
192impl crate::Writable for GLB_PARM_CFG0_SPEC {
193 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
194 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195}
196#[doc = "`reset()` method sets glb_parm_cfg0 to value 0"]
197impl crate::Resettable for GLB_PARM_CFG0_SPEC {
198 const RESET_VALUE: Self::Ux = 0;
199}