bl61x_pac/glb/
digit_clock_1.rs

1#[doc = "Register `digit_clock_1` reader"]
2pub type R = crate::R<DIGIT_CLOCK_1_SPEC>;
3#[doc = "Register `digit_clock_1` writer"]
4pub type W = crate::W<DIGIT_CLOCK_1_SPEC>;
5#[doc = "Field `reg_isp_muxpll_80m_sel` reader - "]
6pub type REG_ISP_MUXPLL_80M_SEL_R = crate::FieldReader;
7#[doc = "Field `reg_isp_muxpll_80m_sel` writer - "]
8pub type REG_ISP_MUXPLL_80M_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `reg_top_muxpll_80m_sel` reader - "]
10pub type REG_TOP_MUXPLL_80M_SEL_R = crate::FieldReader;
11#[doc = "Field `reg_top_muxpll_80m_sel` writer - "]
12pub type REG_TOP_MUXPLL_80M_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `reg_top_muxpll_160m_sel` reader - "]
14pub type REG_TOP_MUXPLL_160M_SEL_R = crate::FieldReader;
15#[doc = "Field `reg_top_muxpll_160m_sel` writer - "]
16pub type REG_TOP_MUXPLL_160M_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    #[doc = "Bits 0:1"]
19    #[inline(always)]
20    pub fn reg_isp_muxpll_80m_sel(&self) -> REG_ISP_MUXPLL_80M_SEL_R {
21        REG_ISP_MUXPLL_80M_SEL_R::new((self.bits & 3) as u8)
22    }
23    #[doc = "Bits 8:9"]
24    #[inline(always)]
25    pub fn reg_top_muxpll_80m_sel(&self) -> REG_TOP_MUXPLL_80M_SEL_R {
26        REG_TOP_MUXPLL_80M_SEL_R::new(((self.bits >> 8) & 3) as u8)
27    }
28    #[doc = "Bits 10:11"]
29    #[inline(always)]
30    pub fn reg_top_muxpll_160m_sel(&self) -> REG_TOP_MUXPLL_160M_SEL_R {
31        REG_TOP_MUXPLL_160M_SEL_R::new(((self.bits >> 10) & 3) as u8)
32    }
33}
34impl W {
35    #[doc = "Bits 0:1"]
36    #[inline(always)]
37    #[must_use]
38    pub fn reg_isp_muxpll_80m_sel(&mut self) -> REG_ISP_MUXPLL_80M_SEL_W<DIGIT_CLOCK_1_SPEC> {
39        REG_ISP_MUXPLL_80M_SEL_W::new(self, 0)
40    }
41    #[doc = "Bits 8:9"]
42    #[inline(always)]
43    #[must_use]
44    pub fn reg_top_muxpll_80m_sel(&mut self) -> REG_TOP_MUXPLL_80M_SEL_W<DIGIT_CLOCK_1_SPEC> {
45        REG_TOP_MUXPLL_80M_SEL_W::new(self, 8)
46    }
47    #[doc = "Bits 10:11"]
48    #[inline(always)]
49    #[must_use]
50    pub fn reg_top_muxpll_160m_sel(&mut self) -> REG_TOP_MUXPLL_160M_SEL_W<DIGIT_CLOCK_1_SPEC> {
51        REG_TOP_MUXPLL_160M_SEL_W::new(self, 10)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "Digital clock configuration 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`digit_clock_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`digit_clock_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct DIGIT_CLOCK_1_SPEC;
66impl crate::RegisterSpec for DIGIT_CLOCK_1_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`digit_clock_1::R`](R) reader structure"]
70impl crate::Readable for DIGIT_CLOCK_1_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`digit_clock_1::W`](W) writer structure"]
72impl crate::Writable for DIGIT_CLOCK_1_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75}
76#[doc = "`reset()` method sets digit_clock_1 to value 0"]
77impl crate::Resettable for DIGIT_CLOCK_1_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
bl61x_pac/glb/digit_clock_1.rs

bl61x_pac/glb/
digit_clock_1.rs
