bl61x_pac/glb/
digit_clock_0.rs1#[doc = "Register `digit_clock_0` reader"]
2pub type R = crate::R<DIGIT_CLOCK_0_SPEC>;
3#[doc = "Register `digit_clock_0` writer"]
4pub type W = crate::W<DIGIT_CLOCK_0_SPEC>;
5#[doc = "Field `dig_32k_div` reader - "]
6pub type DIG_32K_DIV_R = crate::FieldReader<u16>;
7#[doc = "Field `dig_32k_div` writer - "]
8pub type DIG_32K_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 11, u16>;
9#[doc = "Field `dig_32k_en` reader - "]
10pub type DIG_32K_EN_R = crate::BitReader;
11#[doc = "Field `dig_32k_en` writer - "]
12pub type DIG_32K_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `dig_32k_comp` reader - "]
14pub type DIG_32K_COMP_R = crate::BitReader;
15#[doc = "Field `dig_32k_comp` writer - "]
16pub type DIG_32K_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `dig_512k_div` reader - "]
18pub type DIG_512K_DIV_R = crate::FieldReader;
19#[doc = "Field `dig_512k_div` writer - "]
20pub type DIG_512K_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
21#[doc = "Field `dig_512k_en` reader - "]
22pub type DIG_512K_EN_R = crate::BitReader;
23#[doc = "Field `dig_512k_en` writer - "]
24pub type DIG_512K_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `dig_512k_comp` reader - "]
26pub type DIG_512K_COMP_R = crate::BitReader;
27#[doc = "Field `dig_512k_comp` writer - "]
28pub type DIG_512K_COMP_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `dig_clk_src_sel` reader - "]
30pub type DIG_CLK_SRC_SEL_R = crate::FieldReader;
31#[doc = "Field `dig_clk_src_sel` writer - "]
32pub type DIG_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
33#[doc = "Field `reg_en_platform_wakeup` reader - "]
34pub type REG_EN_PLATFORM_WAKEUP_R = crate::BitReader;
35#[doc = "Field `reg_en_platform_wakeup` writer - "]
36pub type REG_EN_PLATFORM_WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bits 0:10"]
39 #[inline(always)]
40 pub fn dig_32k_div(&self) -> DIG_32K_DIV_R {
41 DIG_32K_DIV_R::new((self.bits & 0x07ff) as u16)
42 }
43 #[doc = "Bit 12"]
44 #[inline(always)]
45 pub fn dig_32k_en(&self) -> DIG_32K_EN_R {
46 DIG_32K_EN_R::new(((self.bits >> 12) & 1) != 0)
47 }
48 #[doc = "Bit 13"]
49 #[inline(always)]
50 pub fn dig_32k_comp(&self) -> DIG_32K_COMP_R {
51 DIG_32K_COMP_R::new(((self.bits >> 13) & 1) != 0)
52 }
53 #[doc = "Bits 16:22"]
54 #[inline(always)]
55 pub fn dig_512k_div(&self) -> DIG_512K_DIV_R {
56 DIG_512K_DIV_R::new(((self.bits >> 16) & 0x7f) as u8)
57 }
58 #[doc = "Bit 24"]
59 #[inline(always)]
60 pub fn dig_512k_en(&self) -> DIG_512K_EN_R {
61 DIG_512K_EN_R::new(((self.bits >> 24) & 1) != 0)
62 }
63 #[doc = "Bit 25"]
64 #[inline(always)]
65 pub fn dig_512k_comp(&self) -> DIG_512K_COMP_R {
66 DIG_512K_COMP_R::new(((self.bits >> 25) & 1) != 0)
67 }
68 #[doc = "Bits 28:29"]
69 #[inline(always)]
70 pub fn dig_clk_src_sel(&self) -> DIG_CLK_SRC_SEL_R {
71 DIG_CLK_SRC_SEL_R::new(((self.bits >> 28) & 3) as u8)
72 }
73 #[doc = "Bit 31"]
74 #[inline(always)]
75 pub fn reg_en_platform_wakeup(&self) -> REG_EN_PLATFORM_WAKEUP_R {
76 REG_EN_PLATFORM_WAKEUP_R::new(((self.bits >> 31) & 1) != 0)
77 }
78}
79impl W {
80 #[doc = "Bits 0:10"]
81 #[inline(always)]
82 #[must_use]
83 pub fn dig_32k_div(&mut self) -> DIG_32K_DIV_W<DIGIT_CLOCK_0_SPEC> {
84 DIG_32K_DIV_W::new(self, 0)
85 }
86 #[doc = "Bit 12"]
87 #[inline(always)]
88 #[must_use]
89 pub fn dig_32k_en(&mut self) -> DIG_32K_EN_W<DIGIT_CLOCK_0_SPEC> {
90 DIG_32K_EN_W::new(self, 12)
91 }
92 #[doc = "Bit 13"]
93 #[inline(always)]
94 #[must_use]
95 pub fn dig_32k_comp(&mut self) -> DIG_32K_COMP_W<DIGIT_CLOCK_0_SPEC> {
96 DIG_32K_COMP_W::new(self, 13)
97 }
98 #[doc = "Bits 16:22"]
99 #[inline(always)]
100 #[must_use]
101 pub fn dig_512k_div(&mut self) -> DIG_512K_DIV_W<DIGIT_CLOCK_0_SPEC> {
102 DIG_512K_DIV_W::new(self, 16)
103 }
104 #[doc = "Bit 24"]
105 #[inline(always)]
106 #[must_use]
107 pub fn dig_512k_en(&mut self) -> DIG_512K_EN_W<DIGIT_CLOCK_0_SPEC> {
108 DIG_512K_EN_W::new(self, 24)
109 }
110 #[doc = "Bit 25"]
111 #[inline(always)]
112 #[must_use]
113 pub fn dig_512k_comp(&mut self) -> DIG_512K_COMP_W<DIGIT_CLOCK_0_SPEC> {
114 DIG_512K_COMP_W::new(self, 25)
115 }
116 #[doc = "Bits 28:29"]
117 #[inline(always)]
118 #[must_use]
119 pub fn dig_clk_src_sel(&mut self) -> DIG_CLK_SRC_SEL_W<DIGIT_CLOCK_0_SPEC> {
120 DIG_CLK_SRC_SEL_W::new(self, 28)
121 }
122 #[doc = "Bit 31"]
123 #[inline(always)]
124 #[must_use]
125 pub fn reg_en_platform_wakeup(&mut self) -> REG_EN_PLATFORM_WAKEUP_W<DIGIT_CLOCK_0_SPEC> {
126 REG_EN_PLATFORM_WAKEUP_W::new(self, 31)
127 }
128 #[doc = r" Writes raw bits to the register."]
129 #[doc = r""]
130 #[doc = r" # Safety"]
131 #[doc = r""]
132 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
133 #[inline(always)]
134 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
135 self.bits = bits;
136 self
137 }
138}
139#[doc = "Digital clock configuration 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`digit_clock_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`digit_clock_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
140pub struct DIGIT_CLOCK_0_SPEC;
141impl crate::RegisterSpec for DIGIT_CLOCK_0_SPEC {
142 type Ux = u32;
143}
144#[doc = "`read()` method returns [`digit_clock_0::R`](R) reader structure"]
145impl crate::Readable for DIGIT_CLOCK_0_SPEC {}
146#[doc = "`write(|w| ..)` method takes [`digit_clock_0::W`](W) writer structure"]
147impl crate::Writable for DIGIT_CLOCK_0_SPEC {
148 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
150}
151#[doc = "`reset()` method sets digit_clock_0 to value 0"]
152impl crate::Resettable for DIGIT_CLOCK_0_SPEC {
153 const RESET_VALUE: Self::Ux = 0;
154}