bl61x_pac/glb/
dbi_config.rs

1#[doc = "Register `dbi_config` reader"]
2pub type R = crate::R<DBI_CONFIG_SPEC>;
3#[doc = "Register `dbi_config` writer"]
4pub type W = crate::W<DBI_CONFIG_SPEC>;
5#[doc = "Field `clock_divide` reader - Peripheral clock divide factor"]
6pub type CLOCK_DIVIDE_R = crate::FieldReader;
7#[doc = "Field `clock_divide` writer - Peripheral clock divide factor"]
8pub type CLOCK_DIVIDE_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `clock_enable` reader - Peripheral level clock gate enable"]
10pub type CLOCK_ENABLE_R = crate::BitReader;
11#[doc = "Field `clock_enable` writer - Peripheral level clock gate enable"]
12pub type CLOCK_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `clock_source` reader - Peripheral clock source register"]
14pub type CLOCK_SOURCE_R = crate::BitReader;
15#[doc = "Field `clock_source` writer - Peripheral clock source register"]
16pub type CLOCK_SOURCE_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:4 - Peripheral clock divide factor"]
19    #[inline(always)]
20    pub fn clock_divide(&self) -> CLOCK_DIVIDE_R {
21        CLOCK_DIVIDE_R::new((self.bits & 0x1f) as u8)
22    }
23    #[doc = "Bit 8 - Peripheral level clock gate enable"]
24    #[inline(always)]
25    pub fn clock_enable(&self) -> CLOCK_ENABLE_R {
26        CLOCK_ENABLE_R::new(((self.bits >> 8) & 1) != 0)
27    }
28    #[doc = "Bit 9 - Peripheral clock source register"]
29    #[inline(always)]
30    pub fn clock_source(&self) -> CLOCK_SOURCE_R {
31        CLOCK_SOURCE_R::new(((self.bits >> 9) & 1) != 0)
32    }
33}
34impl W {
35    #[doc = "Bits 0:4 - Peripheral clock divide factor"]
36    #[inline(always)]
37    #[must_use]
38    pub fn clock_divide(&mut self) -> CLOCK_DIVIDE_W<DBI_CONFIG_SPEC> {
39        CLOCK_DIVIDE_W::new(self, 0)
40    }
41    #[doc = "Bit 8 - Peripheral level clock gate enable"]
42    #[inline(always)]
43    #[must_use]
44    pub fn clock_enable(&mut self) -> CLOCK_ENABLE_W<DBI_CONFIG_SPEC> {
45        CLOCK_ENABLE_W::new(self, 8)
46    }
47    #[doc = "Bit 9 - Peripheral clock source register"]
48    #[inline(always)]
49    #[must_use]
50    pub fn clock_source(&mut self) -> CLOCK_SOURCE_W<DBI_CONFIG_SPEC> {
51        CLOCK_SOURCE_W::new(self, 9)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "MIPI Display Bus Interface clock configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dbi_config::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dbi_config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct DBI_CONFIG_SPEC;
66impl crate::RegisterSpec for DBI_CONFIG_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`dbi_config::R`](R) reader structure"]
70impl crate::Readable for DBI_CONFIG_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`dbi_config::W`](W) writer structure"]
72impl crate::Writable for DBI_CONFIG_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75}
76#[doc = "`reset()` method sets dbi_config to value 0"]
77impl crate::Resettable for DBI_CONFIG_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
bl61x_pac/glb/dbi_config.rs

bl61x_pac/glb/
dbi_config.rs
