bl61x_pac/glb/
cgen_cfg3.rs

1#[doc = "Register `cgen_cfg3` reader"]
2pub type R = crate::R<CGEN_CFG3_SPEC>;
3#[doc = "Register `cgen_cfg3` writer"]
4pub type W = crate::W<CGEN_CFG3_SPEC>;
5#[doc = "Field `cgen_isp_wifipll_80m` reader - "]
6pub type CGEN_ISP_WIFIPLL_80M_R = crate::BitReader;
7#[doc = "Field `cgen_isp_wifipll_80m` writer - "]
8pub type CGEN_ISP_WIFIPLL_80M_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `cgen_isp_aupll_div5` reader - "]
10pub type CGEN_ISP_AUPLL_DIV5_R = crate::BitReader;
11#[doc = "Field `cgen_isp_aupll_div5` writer - "]
12pub type CGEN_ISP_AUPLL_DIV5_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `cgen_isp_aupll_div6` reader - "]
14pub type CGEN_ISP_AUPLL_DIV6_R = crate::BitReader;
15#[doc = "Field `cgen_isp_aupll_div6` writer - "]
16pub type CGEN_ISP_AUPLL_DIV6_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `cgen_top_aupll_div5` reader - "]
18pub type CGEN_TOP_AUPLL_DIV5_R = crate::BitReader;
19#[doc = "Field `cgen_top_aupll_div5` writer - "]
20pub type CGEN_TOP_AUPLL_DIV5_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `cgen_top_aupll_div6` reader - "]
22pub type CGEN_TOP_AUPLL_DIV6_R = crate::BitReader;
23#[doc = "Field `cgen_top_aupll_div6` writer - "]
24pub type CGEN_TOP_AUPLL_DIV6_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `cgen_psramB_wifipll_320m` reader - "]
26pub type CGEN_PSRAM_B_WIFIPLL_320M_R = crate::BitReader;
27#[doc = "Field `cgen_psramB_wifipll_320m` writer - "]
28pub type CGEN_PSRAM_B_WIFIPLL_320M_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `cgen_psramB_aupll_div1` reader - "]
30pub type CGEN_PSRAM_B_AUPLL_DIV1_R = crate::BitReader;
31#[doc = "Field `cgen_psramB_aupll_div1` writer - "]
32pub type CGEN_PSRAM_B_AUPLL_DIV1_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `cgen_top_wifipll_240m` reader - "]
34pub type CGEN_TOP_WIFIPLL_240M_R = crate::BitReader;
35#[doc = "Field `cgen_top_wifipll_240m` writer - "]
36pub type CGEN_TOP_WIFIPLL_240M_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `cgen_top_wifipll_320m` reader - "]
38pub type CGEN_TOP_WIFIPLL_320M_R = crate::BitReader;
39#[doc = "Field `cgen_top_wifipll_320m` writer - "]
40pub type CGEN_TOP_WIFIPLL_320M_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `cgen_top_aupll_div2` reader - "]
42pub type CGEN_TOP_AUPLL_DIV2_R = crate::BitReader;
43#[doc = "Field `cgen_top_aupll_div2` writer - "]
44pub type CGEN_TOP_AUPLL_DIV2_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `cgen_top_aupll_div1` reader - "]
46pub type CGEN_TOP_AUPLL_DIV1_R = crate::BitReader;
47#[doc = "Field `cgen_top_aupll_div1` writer - "]
48pub type CGEN_TOP_AUPLL_DIV1_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50    #[doc = "Bit 2"]
51    #[inline(always)]
52    pub fn cgen_isp_wifipll_80m(&self) -> CGEN_ISP_WIFIPLL_80M_R {
53        CGEN_ISP_WIFIPLL_80M_R::new(((self.bits >> 2) & 1) != 0)
54    }
55    #[doc = "Bit 3"]
56    #[inline(always)]
57    pub fn cgen_isp_aupll_div5(&self) -> CGEN_ISP_AUPLL_DIV5_R {
58        CGEN_ISP_AUPLL_DIV5_R::new(((self.bits >> 3) & 1) != 0)
59    }
60    #[doc = "Bit 4"]
61    #[inline(always)]
62    pub fn cgen_isp_aupll_div6(&self) -> CGEN_ISP_AUPLL_DIV6_R {
63        CGEN_ISP_AUPLL_DIV6_R::new(((self.bits >> 4) & 1) != 0)
64    }
65    #[doc = "Bit 5"]
66    #[inline(always)]
67    pub fn cgen_top_aupll_div5(&self) -> CGEN_TOP_AUPLL_DIV5_R {
68        CGEN_TOP_AUPLL_DIV5_R::new(((self.bits >> 5) & 1) != 0)
69    }
70    #[doc = "Bit 6"]
71    #[inline(always)]
72    pub fn cgen_top_aupll_div6(&self) -> CGEN_TOP_AUPLL_DIV6_R {
73        CGEN_TOP_AUPLL_DIV6_R::new(((self.bits >> 6) & 1) != 0)
74    }
75    #[doc = "Bit 7"]
76    #[inline(always)]
77    pub fn cgen_psram_b_wifipll_320m(&self) -> CGEN_PSRAM_B_WIFIPLL_320M_R {
78        CGEN_PSRAM_B_WIFIPLL_320M_R::new(((self.bits >> 7) & 1) != 0)
79    }
80    #[doc = "Bit 8"]
81    #[inline(always)]
82    pub fn cgen_psram_b_aupll_div1(&self) -> CGEN_PSRAM_B_AUPLL_DIV1_R {
83        CGEN_PSRAM_B_AUPLL_DIV1_R::new(((self.bits >> 8) & 1) != 0)
84    }
85    #[doc = "Bit 13"]
86    #[inline(always)]
87    pub fn cgen_top_wifipll_240m(&self) -> CGEN_TOP_WIFIPLL_240M_R {
88        CGEN_TOP_WIFIPLL_240M_R::new(((self.bits >> 13) & 1) != 0)
89    }
90    #[doc = "Bit 14"]
91    #[inline(always)]
92    pub fn cgen_top_wifipll_320m(&self) -> CGEN_TOP_WIFIPLL_320M_R {
93        CGEN_TOP_WIFIPLL_320M_R::new(((self.bits >> 14) & 1) != 0)
94    }
95    #[doc = "Bit 15"]
96    #[inline(always)]
97    pub fn cgen_top_aupll_div2(&self) -> CGEN_TOP_AUPLL_DIV2_R {
98        CGEN_TOP_AUPLL_DIV2_R::new(((self.bits >> 15) & 1) != 0)
99    }
100    #[doc = "Bit 16"]
101    #[inline(always)]
102    pub fn cgen_top_aupll_div1(&self) -> CGEN_TOP_AUPLL_DIV1_R {
103        CGEN_TOP_AUPLL_DIV1_R::new(((self.bits >> 16) & 1) != 0)
104    }
105}
106impl W {
107    #[doc = "Bit 2"]
108    #[inline(always)]
109    #[must_use]
110    pub fn cgen_isp_wifipll_80m(&mut self) -> CGEN_ISP_WIFIPLL_80M_W<CGEN_CFG3_SPEC> {
111        CGEN_ISP_WIFIPLL_80M_W::new(self, 2)
112    }
113    #[doc = "Bit 3"]
114    #[inline(always)]
115    #[must_use]
116    pub fn cgen_isp_aupll_div5(&mut self) -> CGEN_ISP_AUPLL_DIV5_W<CGEN_CFG3_SPEC> {
117        CGEN_ISP_AUPLL_DIV5_W::new(self, 3)
118    }
119    #[doc = "Bit 4"]
120    #[inline(always)]
121    #[must_use]
122    pub fn cgen_isp_aupll_div6(&mut self) -> CGEN_ISP_AUPLL_DIV6_W<CGEN_CFG3_SPEC> {
123        CGEN_ISP_AUPLL_DIV6_W::new(self, 4)
124    }
125    #[doc = "Bit 5"]
126    #[inline(always)]
127    #[must_use]
128    pub fn cgen_top_aupll_div5(&mut self) -> CGEN_TOP_AUPLL_DIV5_W<CGEN_CFG3_SPEC> {
129        CGEN_TOP_AUPLL_DIV5_W::new(self, 5)
130    }
131    #[doc = "Bit 6"]
132    #[inline(always)]
133    #[must_use]
134    pub fn cgen_top_aupll_div6(&mut self) -> CGEN_TOP_AUPLL_DIV6_W<CGEN_CFG3_SPEC> {
135        CGEN_TOP_AUPLL_DIV6_W::new(self, 6)
136    }
137    #[doc = "Bit 7"]
138    #[inline(always)]
139    #[must_use]
140    pub fn cgen_psram_b_wifipll_320m(&mut self) -> CGEN_PSRAM_B_WIFIPLL_320M_W<CGEN_CFG3_SPEC> {
141        CGEN_PSRAM_B_WIFIPLL_320M_W::new(self, 7)
142    }
143    #[doc = "Bit 8"]
144    #[inline(always)]
145    #[must_use]
146    pub fn cgen_psram_b_aupll_div1(&mut self) -> CGEN_PSRAM_B_AUPLL_DIV1_W<CGEN_CFG3_SPEC> {
147        CGEN_PSRAM_B_AUPLL_DIV1_W::new(self, 8)
148    }
149    #[doc = "Bit 13"]
150    #[inline(always)]
151    #[must_use]
152    pub fn cgen_top_wifipll_240m(&mut self) -> CGEN_TOP_WIFIPLL_240M_W<CGEN_CFG3_SPEC> {
153        CGEN_TOP_WIFIPLL_240M_W::new(self, 13)
154    }
155    #[doc = "Bit 14"]
156    #[inline(always)]
157    #[must_use]
158    pub fn cgen_top_wifipll_320m(&mut self) -> CGEN_TOP_WIFIPLL_320M_W<CGEN_CFG3_SPEC> {
159        CGEN_TOP_WIFIPLL_320M_W::new(self, 14)
160    }
161    #[doc = "Bit 15"]
162    #[inline(always)]
163    #[must_use]
164    pub fn cgen_top_aupll_div2(&mut self) -> CGEN_TOP_AUPLL_DIV2_W<CGEN_CFG3_SPEC> {
165        CGEN_TOP_AUPLL_DIV2_W::new(self, 15)
166    }
167    #[doc = "Bit 16"]
168    #[inline(always)]
169    #[must_use]
170    pub fn cgen_top_aupll_div1(&mut self) -> CGEN_TOP_AUPLL_DIV1_W<CGEN_CFG3_SPEC> {
171        CGEN_TOP_AUPLL_DIV1_W::new(self, 16)
172    }
173    #[doc = r" Writes raw bits to the register."]
174    #[doc = r""]
175    #[doc = r" # Safety"]
176    #[doc = r""]
177    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
178    #[inline(always)]
179    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180        self.bits = bits;
181        self
182    }
183}
184#[doc = "cgen_cfg3.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgen_cfg3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgen_cfg3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
185pub struct CGEN_CFG3_SPEC;
186impl crate::RegisterSpec for CGEN_CFG3_SPEC {
187    type Ux = u32;
188}
189#[doc = "`read()` method returns [`cgen_cfg3::R`](R) reader structure"]
190impl crate::Readable for CGEN_CFG3_SPEC {}
191#[doc = "`write(|w| ..)` method takes [`cgen_cfg3::W`](W) writer structure"]
192impl crate::Writable for CGEN_CFG3_SPEC {
193    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
194    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195}
196#[doc = "`reset()` method sets cgen_cfg3 to value 0"]
197impl crate::Resettable for CGEN_CFG3_SPEC {
198    const RESET_VALUE: Self::Ux = 0;
199}
bl61x_pac/glb/cgen_cfg3.rs

bl61x_pac/glb/
cgen_cfg3.rs
