bl61x_pac/glb/
cgen_cfg1.rs1#[doc = "Register `cgen_cfg1` reader"]
2pub type R = crate::R<CGEN_CFG1_SPEC>;
3#[doc = "Register `cgen_cfg1` writer"]
4pub type W = crate::W<CGEN_CFG1_SPEC>;
5#[doc = "Field `cgen_s1_gpip` reader - "]
6pub type CGEN_S1_GPIP_R = crate::BitReader;
7#[doc = "Field `cgen_s1_gpip` writer - "]
8pub type CGEN_S1_GPIP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `cgen_s1_sec_dbg` reader - "]
10pub type CGEN_S1_SEC_DBG_R = crate::BitReader;
11#[doc = "Field `cgen_s1_sec_dbg` writer - "]
12pub type CGEN_S1_SEC_DBG_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `cgen_s1_sec_eng` reader - "]
14pub type CGEN_S1_SEC_ENG_R = crate::BitReader;
15#[doc = "Field `cgen_s1_sec_eng` writer - "]
16pub type CGEN_S1_SEC_ENG_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `cgen_s1_tz` reader - "]
18pub type CGEN_S1_TZ_R = crate::BitReader;
19#[doc = "Field `cgen_s1_tz` writer - "]
20pub type CGEN_S1_TZ_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `cgen_s1_ef_ctrl` reader - "]
22pub type CGEN_S1_EF_CTRL_R = crate::BitReader;
23#[doc = "Field `cgen_s1_ef_ctrl` writer - "]
24pub type CGEN_S1_EF_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `cgen_s1_sf_ctrl` reader - "]
26pub type CGEN_S1_SF_CTRL_R = crate::BitReader;
27#[doc = "Field `cgen_s1_sf_ctrl` writer - "]
28pub type CGEN_S1_SF_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `cgen_s1_dma` reader - "]
30pub type CGEN_S1_DMA_R = crate::BitReader;
31#[doc = "Field `cgen_s1_dma` writer - "]
32pub type CGEN_S1_DMA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `cgen_s1_usb` reader - "]
34pub type CGEN_S1_USB_R = crate::BitReader;
35#[doc = "Field `cgen_s1_usb` writer - "]
36pub type CGEN_S1_USB_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `cgen_s1a_uart0` reader - "]
38pub type CGEN_S1A_UART0_R = crate::BitReader;
39#[doc = "Field `cgen_s1a_uart0` writer - "]
40pub type CGEN_S1A_UART0_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `cgen_s1a_uart1` reader - "]
42pub type CGEN_S1A_UART1_R = crate::BitReader;
43#[doc = "Field `cgen_s1a_uart1` writer - "]
44pub type CGEN_S1A_UART1_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `cgen_s1a_spi` reader - "]
46pub type CGEN_S1A_SPI_R = crate::BitReader;
47#[doc = "Field `cgen_s1a_spi` writer - "]
48pub type CGEN_S1A_SPI_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `cgen_s1a_i2c` reader - "]
50pub type CGEN_S1A_I2C_R = crate::BitReader;
51#[doc = "Field `cgen_s1a_i2c` writer - "]
52pub type CGEN_S1A_I2C_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `cgen_s1a_pwm` reader - "]
54pub type CGEN_S1A_PWM_R = crate::BitReader;
55#[doc = "Field `cgen_s1a_pwm` writer - "]
56pub type CGEN_S1A_PWM_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `cgen_s1a_timer` reader - "]
58pub type CGEN_S1A_TIMER_R = crate::BitReader;
59#[doc = "Field `cgen_s1a_timer` writer - "]
60pub type CGEN_S1A_TIMER_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `cgen_s1a_ir` reader - "]
62pub type CGEN_S1A_IR_R = crate::BitReader;
63#[doc = "Field `cgen_s1a_ir` writer - "]
64pub type CGEN_S1A_IR_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `cgen_s1a_cks` reader - "]
66pub type CGEN_S1A_CKS_R = crate::BitReader;
67#[doc = "Field `cgen_s1a_cks` writer - "]
68pub type CGEN_S1A_CKS_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `cgen_s1a_dbi` reader - "]
70pub type CGEN_S1A_DBI_R = crate::BitReader;
71#[doc = "Field `cgen_s1a_dbi` writer - "]
72pub type CGEN_S1A_DBI_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `cgen_s1a_i2c1` reader - "]
74pub type CGEN_S1A_I2C1_R = crate::BitReader;
75#[doc = "Field `cgen_s1a_i2c1` writer - "]
76pub type CGEN_S1A_I2C1_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `cgen_s1a_uart2` reader - "]
78pub type CGEN_S1A_UART2_R = crate::BitReader;
79#[doc = "Field `cgen_s1a_uart2` writer - "]
80pub type CGEN_S1A_UART2_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `cgen_s1a_i2s` reader - "]
82pub type CGEN_S1A_I2S_R = crate::BitReader;
83#[doc = "Field `cgen_s1a_i2s` writer - "]
84pub type CGEN_S1A_I2S_W<'a, REG> = crate::BitWriter<'a, REG>;
85impl R {
86 #[doc = "Bit 2"]
87 #[inline(always)]
88 pub fn cgen_s1_gpip(&self) -> CGEN_S1_GPIP_R {
89 CGEN_S1_GPIP_R::new(((self.bits >> 2) & 1) != 0)
90 }
91 #[doc = "Bit 3"]
92 #[inline(always)]
93 pub fn cgen_s1_sec_dbg(&self) -> CGEN_S1_SEC_DBG_R {
94 CGEN_S1_SEC_DBG_R::new(((self.bits >> 3) & 1) != 0)
95 }
96 #[doc = "Bit 4"]
97 #[inline(always)]
98 pub fn cgen_s1_sec_eng(&self) -> CGEN_S1_SEC_ENG_R {
99 CGEN_S1_SEC_ENG_R::new(((self.bits >> 4) & 1) != 0)
100 }
101 #[doc = "Bit 5"]
102 #[inline(always)]
103 pub fn cgen_s1_tz(&self) -> CGEN_S1_TZ_R {
104 CGEN_S1_TZ_R::new(((self.bits >> 5) & 1) != 0)
105 }
106 #[doc = "Bit 7"]
107 #[inline(always)]
108 pub fn cgen_s1_ef_ctrl(&self) -> CGEN_S1_EF_CTRL_R {
109 CGEN_S1_EF_CTRL_R::new(((self.bits >> 7) & 1) != 0)
110 }
111 #[doc = "Bit 11"]
112 #[inline(always)]
113 pub fn cgen_s1_sf_ctrl(&self) -> CGEN_S1_SF_CTRL_R {
114 CGEN_S1_SF_CTRL_R::new(((self.bits >> 11) & 1) != 0)
115 }
116 #[doc = "Bit 12"]
117 #[inline(always)]
118 pub fn cgen_s1_dma(&self) -> CGEN_S1_DMA_R {
119 CGEN_S1_DMA_R::new(((self.bits >> 12) & 1) != 0)
120 }
121 #[doc = "Bit 13"]
122 #[inline(always)]
123 pub fn cgen_s1_usb(&self) -> CGEN_S1_USB_R {
124 CGEN_S1_USB_R::new(((self.bits >> 13) & 1) != 0)
125 }
126 #[doc = "Bit 16"]
127 #[inline(always)]
128 pub fn cgen_s1a_uart0(&self) -> CGEN_S1A_UART0_R {
129 CGEN_S1A_UART0_R::new(((self.bits >> 16) & 1) != 0)
130 }
131 #[doc = "Bit 17"]
132 #[inline(always)]
133 pub fn cgen_s1a_uart1(&self) -> CGEN_S1A_UART1_R {
134 CGEN_S1A_UART1_R::new(((self.bits >> 17) & 1) != 0)
135 }
136 #[doc = "Bit 18"]
137 #[inline(always)]
138 pub fn cgen_s1a_spi(&self) -> CGEN_S1A_SPI_R {
139 CGEN_S1A_SPI_R::new(((self.bits >> 18) & 1) != 0)
140 }
141 #[doc = "Bit 19"]
142 #[inline(always)]
143 pub fn cgen_s1a_i2c(&self) -> CGEN_S1A_I2C_R {
144 CGEN_S1A_I2C_R::new(((self.bits >> 19) & 1) != 0)
145 }
146 #[doc = "Bit 20"]
147 #[inline(always)]
148 pub fn cgen_s1a_pwm(&self) -> CGEN_S1A_PWM_R {
149 CGEN_S1A_PWM_R::new(((self.bits >> 20) & 1) != 0)
150 }
151 #[doc = "Bit 21"]
152 #[inline(always)]
153 pub fn cgen_s1a_timer(&self) -> CGEN_S1A_TIMER_R {
154 CGEN_S1A_TIMER_R::new(((self.bits >> 21) & 1) != 0)
155 }
156 #[doc = "Bit 22"]
157 #[inline(always)]
158 pub fn cgen_s1a_ir(&self) -> CGEN_S1A_IR_R {
159 CGEN_S1A_IR_R::new(((self.bits >> 22) & 1) != 0)
160 }
161 #[doc = "Bit 23"]
162 #[inline(always)]
163 pub fn cgen_s1a_cks(&self) -> CGEN_S1A_CKS_R {
164 CGEN_S1A_CKS_R::new(((self.bits >> 23) & 1) != 0)
165 }
166 #[doc = "Bit 24"]
167 #[inline(always)]
168 pub fn cgen_s1a_dbi(&self) -> CGEN_S1A_DBI_R {
169 CGEN_S1A_DBI_R::new(((self.bits >> 24) & 1) != 0)
170 }
171 #[doc = "Bit 25"]
172 #[inline(always)]
173 pub fn cgen_s1a_i2c1(&self) -> CGEN_S1A_I2C1_R {
174 CGEN_S1A_I2C1_R::new(((self.bits >> 25) & 1) != 0)
175 }
176 #[doc = "Bit 26"]
177 #[inline(always)]
178 pub fn cgen_s1a_uart2(&self) -> CGEN_S1A_UART2_R {
179 CGEN_S1A_UART2_R::new(((self.bits >> 26) & 1) != 0)
180 }
181 #[doc = "Bit 27"]
182 #[inline(always)]
183 pub fn cgen_s1a_i2s(&self) -> CGEN_S1A_I2S_R {
184 CGEN_S1A_I2S_R::new(((self.bits >> 27) & 1) != 0)
185 }
186}
187impl W {
188 #[doc = "Bit 2"]
189 #[inline(always)]
190 #[must_use]
191 pub fn cgen_s1_gpip(&mut self) -> CGEN_S1_GPIP_W<CGEN_CFG1_SPEC> {
192 CGEN_S1_GPIP_W::new(self, 2)
193 }
194 #[doc = "Bit 3"]
195 #[inline(always)]
196 #[must_use]
197 pub fn cgen_s1_sec_dbg(&mut self) -> CGEN_S1_SEC_DBG_W<CGEN_CFG1_SPEC> {
198 CGEN_S1_SEC_DBG_W::new(self, 3)
199 }
200 #[doc = "Bit 4"]
201 #[inline(always)]
202 #[must_use]
203 pub fn cgen_s1_sec_eng(&mut self) -> CGEN_S1_SEC_ENG_W<CGEN_CFG1_SPEC> {
204 CGEN_S1_SEC_ENG_W::new(self, 4)
205 }
206 #[doc = "Bit 5"]
207 #[inline(always)]
208 #[must_use]
209 pub fn cgen_s1_tz(&mut self) -> CGEN_S1_TZ_W<CGEN_CFG1_SPEC> {
210 CGEN_S1_TZ_W::new(self, 5)
211 }
212 #[doc = "Bit 7"]
213 #[inline(always)]
214 #[must_use]
215 pub fn cgen_s1_ef_ctrl(&mut self) -> CGEN_S1_EF_CTRL_W<CGEN_CFG1_SPEC> {
216 CGEN_S1_EF_CTRL_W::new(self, 7)
217 }
218 #[doc = "Bit 11"]
219 #[inline(always)]
220 #[must_use]
221 pub fn cgen_s1_sf_ctrl(&mut self) -> CGEN_S1_SF_CTRL_W<CGEN_CFG1_SPEC> {
222 CGEN_S1_SF_CTRL_W::new(self, 11)
223 }
224 #[doc = "Bit 12"]
225 #[inline(always)]
226 #[must_use]
227 pub fn cgen_s1_dma(&mut self) -> CGEN_S1_DMA_W<CGEN_CFG1_SPEC> {
228 CGEN_S1_DMA_W::new(self, 12)
229 }
230 #[doc = "Bit 13"]
231 #[inline(always)]
232 #[must_use]
233 pub fn cgen_s1_usb(&mut self) -> CGEN_S1_USB_W<CGEN_CFG1_SPEC> {
234 CGEN_S1_USB_W::new(self, 13)
235 }
236 #[doc = "Bit 16"]
237 #[inline(always)]
238 #[must_use]
239 pub fn cgen_s1a_uart0(&mut self) -> CGEN_S1A_UART0_W<CGEN_CFG1_SPEC> {
240 CGEN_S1A_UART0_W::new(self, 16)
241 }
242 #[doc = "Bit 17"]
243 #[inline(always)]
244 #[must_use]
245 pub fn cgen_s1a_uart1(&mut self) -> CGEN_S1A_UART1_W<CGEN_CFG1_SPEC> {
246 CGEN_S1A_UART1_W::new(self, 17)
247 }
248 #[doc = "Bit 18"]
249 #[inline(always)]
250 #[must_use]
251 pub fn cgen_s1a_spi(&mut self) -> CGEN_S1A_SPI_W<CGEN_CFG1_SPEC> {
252 CGEN_S1A_SPI_W::new(self, 18)
253 }
254 #[doc = "Bit 19"]
255 #[inline(always)]
256 #[must_use]
257 pub fn cgen_s1a_i2c(&mut self) -> CGEN_S1A_I2C_W<CGEN_CFG1_SPEC> {
258 CGEN_S1A_I2C_W::new(self, 19)
259 }
260 #[doc = "Bit 20"]
261 #[inline(always)]
262 #[must_use]
263 pub fn cgen_s1a_pwm(&mut self) -> CGEN_S1A_PWM_W<CGEN_CFG1_SPEC> {
264 CGEN_S1A_PWM_W::new(self, 20)
265 }
266 #[doc = "Bit 21"]
267 #[inline(always)]
268 #[must_use]
269 pub fn cgen_s1a_timer(&mut self) -> CGEN_S1A_TIMER_W<CGEN_CFG1_SPEC> {
270 CGEN_S1A_TIMER_W::new(self, 21)
271 }
272 #[doc = "Bit 22"]
273 #[inline(always)]
274 #[must_use]
275 pub fn cgen_s1a_ir(&mut self) -> CGEN_S1A_IR_W<CGEN_CFG1_SPEC> {
276 CGEN_S1A_IR_W::new(self, 22)
277 }
278 #[doc = "Bit 23"]
279 #[inline(always)]
280 #[must_use]
281 pub fn cgen_s1a_cks(&mut self) -> CGEN_S1A_CKS_W<CGEN_CFG1_SPEC> {
282 CGEN_S1A_CKS_W::new(self, 23)
283 }
284 #[doc = "Bit 24"]
285 #[inline(always)]
286 #[must_use]
287 pub fn cgen_s1a_dbi(&mut self) -> CGEN_S1A_DBI_W<CGEN_CFG1_SPEC> {
288 CGEN_S1A_DBI_W::new(self, 24)
289 }
290 #[doc = "Bit 25"]
291 #[inline(always)]
292 #[must_use]
293 pub fn cgen_s1a_i2c1(&mut self) -> CGEN_S1A_I2C1_W<CGEN_CFG1_SPEC> {
294 CGEN_S1A_I2C1_W::new(self, 25)
295 }
296 #[doc = "Bit 26"]
297 #[inline(always)]
298 #[must_use]
299 pub fn cgen_s1a_uart2(&mut self) -> CGEN_S1A_UART2_W<CGEN_CFG1_SPEC> {
300 CGEN_S1A_UART2_W::new(self, 26)
301 }
302 #[doc = "Bit 27"]
303 #[inline(always)]
304 #[must_use]
305 pub fn cgen_s1a_i2s(&mut self) -> CGEN_S1A_I2S_W<CGEN_CFG1_SPEC> {
306 CGEN_S1A_I2S_W::new(self, 27)
307 }
308 #[doc = r" Writes raw bits to the register."]
309 #[doc = r""]
310 #[doc = r" # Safety"]
311 #[doc = r""]
312 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
313 #[inline(always)]
314 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
315 self.bits = bits;
316 self
317 }
318}
319#[doc = "cgen_s1a + cgen_s1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgen_cfg1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgen_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
320pub struct CGEN_CFG1_SPEC;
321impl crate::RegisterSpec for CGEN_CFG1_SPEC {
322 type Ux = u32;
323}
324#[doc = "`read()` method returns [`cgen_cfg1::R`](R) reader structure"]
325impl crate::Readable for CGEN_CFG1_SPEC {}
326#[doc = "`write(|w| ..)` method takes [`cgen_cfg1::W`](W) writer structure"]
327impl crate::Writable for CGEN_CFG1_SPEC {
328 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
329 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
330}
331#[doc = "`reset()` method sets cgen_cfg1 to value 0"]
332impl crate::Resettable for CGEN_CFG1_SPEC {
333 const RESET_VALUE: Self::Ux = 0;
334}