bl61x_pac/dma/channel/
config.rs1#[doc = "Register `config` reader"]
2pub type R = crate::R<CONFIG_SPEC>;
3#[doc = "Register `config` writer"]
4pub type W = crate::W<CONFIG_SPEC>;
5#[doc = "Field `function` reader - Enable or disable DMA channel"]
6pub type FUNCTION_R = crate::BitReader;
7#[doc = "Field `function` writer - Enable or disable DMA channel"]
8pub type FUNCTION_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `source_peripheral` reader - Set source peripheral for this DMA channel"]
10pub type SOURCE_PERIPHERAL_R = crate::FieldReader;
11#[doc = "Field `source_peripheral` writer - Set source peripheral for this DMA channel"]
12pub type SOURCE_PERIPHERAL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13#[doc = "Field `destination_peripheral` reader - Set destination peripheral for this DMA channel"]
14pub type DESTINATION_PERIPHERAL_R = crate::FieldReader;
15#[doc = "Field `destination_peripheral` writer - Set destination peripheral for this DMA channel"]
16pub type DESTINATION_PERIPHERAL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
17#[doc = "Field `flow_control` reader - Set data direction for this channel"]
18pub type FLOW_CONTROL_R = crate::FieldReader;
19#[doc = "Field `flow_control` writer - Set data direction for this channel"]
20pub type FLOW_CONTROL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `error_mask` reader - Mask error interrupt"]
22pub type ERROR_MASK_R = crate::BitReader;
23#[doc = "Field `error_mask` writer - Mask error interrupt"]
24pub type ERROR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `terminate_mask` reader - Mask terminal count interrupt"]
26pub type TERMINATE_MASK_R = crate::BitReader;
27#[doc = "Field `terminate_mask` writer - Mask terminal count interrupt"]
28pub type TERMINATE_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `active` reader - ??"]
30pub type ACTIVE_R = crate::BitReader;
31#[doc = "Field `lock` reader - ??"]
32pub type LOCK_R = crate::BitReader;
33#[doc = "Field `lock` writer - ??"]
34pub type LOCK_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `halt` reader - ??"]
36pub type HALT_R = crate::BitReader;
37#[doc = "Field `halt` writer - ??"]
38pub type HALT_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `linked_list_counter` reader - ??"]
40pub type LINKED_LIST_COUNTER_R = crate::FieldReader<u16>;
41#[doc = "Field `linked_list_counter` writer - ??"]
42pub type LINKED_LIST_COUNTER_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
43impl R {
44 #[doc = "Bit 0 - Enable or disable DMA channel"]
45 #[inline(always)]
46 pub fn function(&self) -> FUNCTION_R {
47 FUNCTION_R::new((self.bits & 1) != 0)
48 }
49 #[doc = "Bits 1:5 - Set source peripheral for this DMA channel"]
50 #[inline(always)]
51 pub fn source_peripheral(&self) -> SOURCE_PERIPHERAL_R {
52 SOURCE_PERIPHERAL_R::new(((self.bits >> 1) & 0x1f) as u8)
53 }
54 #[doc = "Bits 6:10 - Set destination peripheral for this DMA channel"]
55 #[inline(always)]
56 pub fn destination_peripheral(&self) -> DESTINATION_PERIPHERAL_R {
57 DESTINATION_PERIPHERAL_R::new(((self.bits >> 6) & 0x1f) as u8)
58 }
59 #[doc = "Bits 11:13 - Set data direction for this channel"]
60 #[inline(always)]
61 pub fn flow_control(&self) -> FLOW_CONTROL_R {
62 FLOW_CONTROL_R::new(((self.bits >> 11) & 7) as u8)
63 }
64 #[doc = "Bit 14 - Mask error interrupt"]
65 #[inline(always)]
66 pub fn error_mask(&self) -> ERROR_MASK_R {
67 ERROR_MASK_R::new(((self.bits >> 14) & 1) != 0)
68 }
69 #[doc = "Bit 15 - Mask terminal count interrupt"]
70 #[inline(always)]
71 pub fn terminate_mask(&self) -> TERMINATE_MASK_R {
72 TERMINATE_MASK_R::new(((self.bits >> 15) & 1) != 0)
73 }
74 #[doc = "Bit 16 - ??"]
75 #[inline(always)]
76 pub fn active(&self) -> ACTIVE_R {
77 ACTIVE_R::new(((self.bits >> 16) & 1) != 0)
78 }
79 #[doc = "Bit 16 - ??"]
80 #[inline(always)]
81 pub fn lock(&self) -> LOCK_R {
82 LOCK_R::new(((self.bits >> 16) & 1) != 0)
83 }
84 #[doc = "Bit 17 - ??"]
85 #[inline(always)]
86 pub fn halt(&self) -> HALT_R {
87 HALT_R::new(((self.bits >> 17) & 1) != 0)
88 }
89 #[doc = "Bits 20:29 - ??"]
90 #[inline(always)]
91 pub fn linked_list_counter(&self) -> LINKED_LIST_COUNTER_R {
92 LINKED_LIST_COUNTER_R::new(((self.bits >> 20) & 0x03ff) as u16)
93 }
94}
95impl W {
96 #[doc = "Bit 0 - Enable or disable DMA channel"]
97 #[inline(always)]
98 #[must_use]
99 pub fn function(&mut self) -> FUNCTION_W<CONFIG_SPEC> {
100 FUNCTION_W::new(self, 0)
101 }
102 #[doc = "Bits 1:5 - Set source peripheral for this DMA channel"]
103 #[inline(always)]
104 #[must_use]
105 pub fn source_peripheral(&mut self) -> SOURCE_PERIPHERAL_W<CONFIG_SPEC> {
106 SOURCE_PERIPHERAL_W::new(self, 1)
107 }
108 #[doc = "Bits 6:10 - Set destination peripheral for this DMA channel"]
109 #[inline(always)]
110 #[must_use]
111 pub fn destination_peripheral(&mut self) -> DESTINATION_PERIPHERAL_W<CONFIG_SPEC> {
112 DESTINATION_PERIPHERAL_W::new(self, 6)
113 }
114 #[doc = "Bits 11:13 - Set data direction for this channel"]
115 #[inline(always)]
116 #[must_use]
117 pub fn flow_control(&mut self) -> FLOW_CONTROL_W<CONFIG_SPEC> {
118 FLOW_CONTROL_W::new(self, 11)
119 }
120 #[doc = "Bit 14 - Mask error interrupt"]
121 #[inline(always)]
122 #[must_use]
123 pub fn error_mask(&mut self) -> ERROR_MASK_W<CONFIG_SPEC> {
124 ERROR_MASK_W::new(self, 14)
125 }
126 #[doc = "Bit 15 - Mask terminal count interrupt"]
127 #[inline(always)]
128 #[must_use]
129 pub fn terminate_mask(&mut self) -> TERMINATE_MASK_W<CONFIG_SPEC> {
130 TERMINATE_MASK_W::new(self, 15)
131 }
132 #[doc = "Bit 16 - ??"]
133 #[inline(always)]
134 #[must_use]
135 pub fn lock(&mut self) -> LOCK_W<CONFIG_SPEC> {
136 LOCK_W::new(self, 16)
137 }
138 #[doc = "Bit 17 - ??"]
139 #[inline(always)]
140 #[must_use]
141 pub fn halt(&mut self) -> HALT_W<CONFIG_SPEC> {
142 HALT_W::new(self, 17)
143 }
144 #[doc = "Bits 20:29 - ??"]
145 #[inline(always)]
146 #[must_use]
147 pub fn linked_list_counter(&mut self) -> LINKED_LIST_COUNTER_W<CONFIG_SPEC> {
148 LINKED_LIST_COUNTER_W::new(self, 20)
149 }
150 #[doc = r" Writes raw bits to the register."]
151 #[doc = r""]
152 #[doc = r" # Safety"]
153 #[doc = r""]
154 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
155 #[inline(always)]
156 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
157 self.bits = bits;
158 self
159 }
160}
161#[doc = "Configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
162pub struct CONFIG_SPEC;
163impl crate::RegisterSpec for CONFIG_SPEC {
164 type Ux = u32;
165}
166#[doc = "`read()` method returns [`config::R`](R) reader structure"]
167impl crate::Readable for CONFIG_SPEC {}
168#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
169impl crate::Writable for CONFIG_SPEC {
170 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
171 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
172}
173#[doc = "`reset()` method sets config to value 0"]
174impl crate::Resettable for CONFIG_SPEC {
175 const RESET_VALUE: Self::Ux = 0;
176}