bl61x_pac/cci/
audio_pll_cfg9.rs

1#[doc = "Register `audio_pll_cfg9` reader"]
2pub type R = crate::R<AUDIO_PLL_CFG9_SPEC>;
3#[doc = "Register `audio_pll_cfg9` writer"]
4pub type W = crate::W<AUDIO_PLL_CFG9_SPEC>;
5#[doc = "Field `aupll_dc_tp_out_en` reader - "]
6pub type AUPLL_DC_TP_OUT_EN_R = crate::BitReader;
7#[doc = "Field `aupll_dc_tp_out_en` writer - "]
8pub type AUPLL_DC_TP_OUT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ten_aupll` reader - "]
10pub type TEN_AUPLL_R = crate::BitReader;
11#[doc = "Field `ten_aupll` writer - "]
12pub type TEN_AUPLL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ten_aupll_sfreg` reader - "]
14pub type TEN_AUPLL_SFREG_R = crate::BitReader;
15#[doc = "Field `ten_aupll_sfreg` writer - "]
16pub type TEN_AUPLL_SFREG_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `dten_aupll_fin` reader - "]
18pub type DTEN_AUPLL_FIN_R = crate::BitReader;
19#[doc = "Field `dten_aupll_fin` writer - "]
20pub type DTEN_AUPLL_FIN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `dten_aupll_fref` reader - "]
22pub type DTEN_AUPLL_FREF_R = crate::BitReader;
23#[doc = "Field `dten_aupll_fref` writer - "]
24pub type DTEN_AUPLL_FREF_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `dten_aupll_fsdm` reader - "]
26pub type DTEN_AUPLL_FSDM_R = crate::BitReader;
27#[doc = "Field `dten_aupll_fsdm` writer - "]
28pub type DTEN_AUPLL_FSDM_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `dten_aupll_div15` reader - "]
30pub type DTEN_AUPLL_DIV15_R = crate::BitReader;
31#[doc = "Field `dten_aupll_div15` writer - "]
32pub type DTEN_AUPLL_DIV15_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `dten_aupll_div5` reader - "]
34pub type DTEN_AUPLL_DIV5_R = crate::BitReader;
35#[doc = "Field `dten_aupll_div5` writer - "]
36pub type DTEN_AUPLL_DIV5_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `dten_aupll_postdiv_clk` reader - "]
38pub type DTEN_AUPLL_POSTDIV_CLK_R = crate::BitReader;
39#[doc = "Field `dten_aupll_postdiv_clk` writer - "]
40pub type DTEN_AUPLL_POSTDIV_CLK_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `dtest_aupll_pulldown` reader - "]
42pub type DTEST_AUPLL_PULLDOWN_R = crate::BitReader;
43#[doc = "Field `dtest_aupll_pulldown` writer - "]
44pub type DTEST_AUPLL_PULLDOWN_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46    #[doc = "Bit 0"]
47    #[inline(always)]
48    pub fn aupll_dc_tp_out_en(&self) -> AUPLL_DC_TP_OUT_EN_R {
49        AUPLL_DC_TP_OUT_EN_R::new((self.bits & 1) != 0)
50    }
51    #[doc = "Bit 1"]
52    #[inline(always)]
53    pub fn ten_aupll(&self) -> TEN_AUPLL_R {
54        TEN_AUPLL_R::new(((self.bits >> 1) & 1) != 0)
55    }
56    #[doc = "Bit 2"]
57    #[inline(always)]
58    pub fn ten_aupll_sfreg(&self) -> TEN_AUPLL_SFREG_R {
59        TEN_AUPLL_SFREG_R::new(((self.bits >> 2) & 1) != 0)
60    }
61    #[doc = "Bit 4"]
62    #[inline(always)]
63    pub fn dten_aupll_fin(&self) -> DTEN_AUPLL_FIN_R {
64        DTEN_AUPLL_FIN_R::new(((self.bits >> 4) & 1) != 0)
65    }
66    #[doc = "Bit 5"]
67    #[inline(always)]
68    pub fn dten_aupll_fref(&self) -> DTEN_AUPLL_FREF_R {
69        DTEN_AUPLL_FREF_R::new(((self.bits >> 5) & 1) != 0)
70    }
71    #[doc = "Bit 6"]
72    #[inline(always)]
73    pub fn dten_aupll_fsdm(&self) -> DTEN_AUPLL_FSDM_R {
74        DTEN_AUPLL_FSDM_R::new(((self.bits >> 6) & 1) != 0)
75    }
76    #[doc = "Bit 7"]
77    #[inline(always)]
78    pub fn dten_aupll_div15(&self) -> DTEN_AUPLL_DIV15_R {
79        DTEN_AUPLL_DIV15_R::new(((self.bits >> 7) & 1) != 0)
80    }
81    #[doc = "Bit 8"]
82    #[inline(always)]
83    pub fn dten_aupll_div5(&self) -> DTEN_AUPLL_DIV5_R {
84        DTEN_AUPLL_DIV5_R::new(((self.bits >> 8) & 1) != 0)
85    }
86    #[doc = "Bit 9"]
87    #[inline(always)]
88    pub fn dten_aupll_postdiv_clk(&self) -> DTEN_AUPLL_POSTDIV_CLK_R {
89        DTEN_AUPLL_POSTDIV_CLK_R::new(((self.bits >> 9) & 1) != 0)
90    }
91    #[doc = "Bit 10"]
92    #[inline(always)]
93    pub fn dtest_aupll_pulldown(&self) -> DTEST_AUPLL_PULLDOWN_R {
94        DTEST_AUPLL_PULLDOWN_R::new(((self.bits >> 10) & 1) != 0)
95    }
96}
97impl W {
98    #[doc = "Bit 0"]
99    #[inline(always)]
100    #[must_use]
101    pub fn aupll_dc_tp_out_en(&mut self) -> AUPLL_DC_TP_OUT_EN_W<AUDIO_PLL_CFG9_SPEC> {
102        AUPLL_DC_TP_OUT_EN_W::new(self, 0)
103    }
104    #[doc = "Bit 1"]
105    #[inline(always)]
106    #[must_use]
107    pub fn ten_aupll(&mut self) -> TEN_AUPLL_W<AUDIO_PLL_CFG9_SPEC> {
108        TEN_AUPLL_W::new(self, 1)
109    }
110    #[doc = "Bit 2"]
111    #[inline(always)]
112    #[must_use]
113    pub fn ten_aupll_sfreg(&mut self) -> TEN_AUPLL_SFREG_W<AUDIO_PLL_CFG9_SPEC> {
114        TEN_AUPLL_SFREG_W::new(self, 2)
115    }
116    #[doc = "Bit 4"]
117    #[inline(always)]
118    #[must_use]
119    pub fn dten_aupll_fin(&mut self) -> DTEN_AUPLL_FIN_W<AUDIO_PLL_CFG9_SPEC> {
120        DTEN_AUPLL_FIN_W::new(self, 4)
121    }
122    #[doc = "Bit 5"]
123    #[inline(always)]
124    #[must_use]
125    pub fn dten_aupll_fref(&mut self) -> DTEN_AUPLL_FREF_W<AUDIO_PLL_CFG9_SPEC> {
126        DTEN_AUPLL_FREF_W::new(self, 5)
127    }
128    #[doc = "Bit 6"]
129    #[inline(always)]
130    #[must_use]
131    pub fn dten_aupll_fsdm(&mut self) -> DTEN_AUPLL_FSDM_W<AUDIO_PLL_CFG9_SPEC> {
132        DTEN_AUPLL_FSDM_W::new(self, 6)
133    }
134    #[doc = "Bit 7"]
135    #[inline(always)]
136    #[must_use]
137    pub fn dten_aupll_div15(&mut self) -> DTEN_AUPLL_DIV15_W<AUDIO_PLL_CFG9_SPEC> {
138        DTEN_AUPLL_DIV15_W::new(self, 7)
139    }
140    #[doc = "Bit 8"]
141    #[inline(always)]
142    #[must_use]
143    pub fn dten_aupll_div5(&mut self) -> DTEN_AUPLL_DIV5_W<AUDIO_PLL_CFG9_SPEC> {
144        DTEN_AUPLL_DIV5_W::new(self, 8)
145    }
146    #[doc = "Bit 9"]
147    #[inline(always)]
148    #[must_use]
149    pub fn dten_aupll_postdiv_clk(&mut self) -> DTEN_AUPLL_POSTDIV_CLK_W<AUDIO_PLL_CFG9_SPEC> {
150        DTEN_AUPLL_POSTDIV_CLK_W::new(self, 9)
151    }
152    #[doc = "Bit 10"]
153    #[inline(always)]
154    #[must_use]
155    pub fn dtest_aupll_pulldown(&mut self) -> DTEST_AUPLL_PULLDOWN_W<AUDIO_PLL_CFG9_SPEC> {
156        DTEST_AUPLL_PULLDOWN_W::new(self, 10)
157    }
158    #[doc = r" Writes raw bits to the register."]
159    #[doc = r""]
160    #[doc = r" # Safety"]
161    #[doc = r""]
162    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
163    #[inline(always)]
164    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
165        self.bits = bits;
166        self
167    }
168}
169#[doc = "audio_pll_cfg9.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`audio_pll_cfg9::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`audio_pll_cfg9::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
170pub struct AUDIO_PLL_CFG9_SPEC;
171impl crate::RegisterSpec for AUDIO_PLL_CFG9_SPEC {
172    type Ux = u32;
173}
174#[doc = "`read()` method returns [`audio_pll_cfg9::R`](R) reader structure"]
175impl crate::Readable for AUDIO_PLL_CFG9_SPEC {}
176#[doc = "`write(|w| ..)` method takes [`audio_pll_cfg9::W`](W) writer structure"]
177impl crate::Writable for AUDIO_PLL_CFG9_SPEC {
178    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
179    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180}
181#[doc = "`reset()` method sets audio_pll_cfg9 to value 0"]
182impl crate::Resettable for AUDIO_PLL_CFG9_SPEC {
183    const RESET_VALUE: Self::Ux = 0;
184}
bl61x_pac/cci/audio_pll_cfg9.rs

bl61x_pac/cci/
audio_pll_cfg9.rs
