bl61x_pac/aon/
dcdc_top_0.rs1#[doc = "Register `dcdc_top_0` reader"]
2pub type R = crate::R<DCDC_TOP_0_SPEC>;
3#[doc = "Register `dcdc_top_0` writer"]
4pub type W = crate::W<DCDC_TOP_0_SPEC>;
5#[doc = "Field `dcdc_vout_sel_aon` reader - "]
6pub type DCDC_VOUT_SEL_AON_R = crate::FieldReader;
7#[doc = "Field `dcdc_vout_sel_aon` writer - "]
8pub type DCDC_VOUT_SEL_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `dcdc_vpfm_aon` reader - "]
10pub type DCDC_VPFM_AON_R = crate::FieldReader;
11#[doc = "Field `dcdc_vpfm_aon` writer - "]
12pub type DCDC_VPFM_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `dcdc_osc_2m_mode_aon` reader - "]
14pub type DCDC_OSC_2M_MODE_AON_R = crate::BitReader;
15#[doc = "Field `dcdc_osc_2m_mode_aon` writer - "]
16pub type DCDC_OSC_2M_MODE_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `dcdc_osc_freq_trim_aon` reader - "]
18pub type DCDC_OSC_FREQ_TRIM_AON_R = crate::FieldReader;
19#[doc = "Field `dcdc_osc_freq_trim_aon` writer - "]
20pub type DCDC_OSC_FREQ_TRIM_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `dcdc_slope_curr_sel_aon` reader - "]
22pub type DCDC_SLOPE_CURR_SEL_AON_R = crate::FieldReader;
23#[doc = "Field `dcdc_slope_curr_sel_aon` writer - "]
24pub type DCDC_SLOPE_CURR_SEL_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
25#[doc = "Field `dcdc_en_stop_osc_aon` reader - "]
26pub type DCDC_EN_STOP_OSC_AON_R = crate::BitReader;
27#[doc = "Field `dcdc_en_stop_osc_aon` writer - "]
28pub type DCDC_EN_STOP_OSC_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `dcdc_en_slow_osc_aon` reader - "]
30pub type DCDC_EN_SLOW_OSC_AON_R = crate::BitReader;
31#[doc = "Field `dcdc_en_slow_osc_aon` writer - "]
32pub type DCDC_EN_SLOW_OSC_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `dcdc_en_osc_inhibit_t2_aon` reader - "]
34pub type DCDC_EN_OSC_INHIBIT_T2_AON_R = crate::BitReader;
35#[doc = "Field `dcdc_en_osc_inhibit_t2_aon` writer - "]
36pub type DCDC_EN_OSC_INHIBIT_T2_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `dcdc_sstart_time_aon` reader - "]
38pub type DCDC_SSTART_TIME_AON_R = crate::FieldReader;
39#[doc = "Field `dcdc_sstart_time_aon` writer - "]
40pub type DCDC_SSTART_TIME_AON_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
41#[doc = "Field `dcdc_dis_aon` reader - "]
42pub type DCDC_DIS_AON_R = crate::BitReader;
43#[doc = "Field `dcdc_dis_aon` writer - "]
44pub type DCDC_DIS_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `dcdc_rdy_aon` reader - "]
46pub type DCDC_RDY_AON_R = crate::BitReader;
47#[doc = "Field `dcdc_rdy_aon` writer - "]
48pub type DCDC_RDY_AON_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bits 0:4"]
51 #[inline(always)]
52 pub fn dcdc_vout_sel_aon(&self) -> DCDC_VOUT_SEL_AON_R {
53 DCDC_VOUT_SEL_AON_R::new((self.bits & 0x1f) as u8)
54 }
55 #[doc = "Bits 8:11"]
56 #[inline(always)]
57 pub fn dcdc_vpfm_aon(&self) -> DCDC_VPFM_AON_R {
58 DCDC_VPFM_AON_R::new(((self.bits >> 8) & 0x0f) as u8)
59 }
60 #[doc = "Bit 12"]
61 #[inline(always)]
62 pub fn dcdc_osc_2m_mode_aon(&self) -> DCDC_OSC_2M_MODE_AON_R {
63 DCDC_OSC_2M_MODE_AON_R::new(((self.bits >> 12) & 1) != 0)
64 }
65 #[doc = "Bits 16:19"]
66 #[inline(always)]
67 pub fn dcdc_osc_freq_trim_aon(&self) -> DCDC_OSC_FREQ_TRIM_AON_R {
68 DCDC_OSC_FREQ_TRIM_AON_R::new(((self.bits >> 16) & 0x0f) as u8)
69 }
70 #[doc = "Bits 20:24"]
71 #[inline(always)]
72 pub fn dcdc_slope_curr_sel_aon(&self) -> DCDC_SLOPE_CURR_SEL_AON_R {
73 DCDC_SLOPE_CURR_SEL_AON_R::new(((self.bits >> 20) & 0x1f) as u8)
74 }
75 #[doc = "Bit 25"]
76 #[inline(always)]
77 pub fn dcdc_en_stop_osc_aon(&self) -> DCDC_EN_STOP_OSC_AON_R {
78 DCDC_EN_STOP_OSC_AON_R::new(((self.bits >> 25) & 1) != 0)
79 }
80 #[doc = "Bit 26"]
81 #[inline(always)]
82 pub fn dcdc_en_slow_osc_aon(&self) -> DCDC_EN_SLOW_OSC_AON_R {
83 DCDC_EN_SLOW_OSC_AON_R::new(((self.bits >> 26) & 1) != 0)
84 }
85 #[doc = "Bit 27"]
86 #[inline(always)]
87 pub fn dcdc_en_osc_inhibit_t2_aon(&self) -> DCDC_EN_OSC_INHIBIT_T2_AON_R {
88 DCDC_EN_OSC_INHIBIT_T2_AON_R::new(((self.bits >> 27) & 1) != 0)
89 }
90 #[doc = "Bits 28:29"]
91 #[inline(always)]
92 pub fn dcdc_sstart_time_aon(&self) -> DCDC_SSTART_TIME_AON_R {
93 DCDC_SSTART_TIME_AON_R::new(((self.bits >> 28) & 3) as u8)
94 }
95 #[doc = "Bit 30"]
96 #[inline(always)]
97 pub fn dcdc_dis_aon(&self) -> DCDC_DIS_AON_R {
98 DCDC_DIS_AON_R::new(((self.bits >> 30) & 1) != 0)
99 }
100 #[doc = "Bit 31"]
101 #[inline(always)]
102 pub fn dcdc_rdy_aon(&self) -> DCDC_RDY_AON_R {
103 DCDC_RDY_AON_R::new(((self.bits >> 31) & 1) != 0)
104 }
105}
106impl W {
107 #[doc = "Bits 0:4"]
108 #[inline(always)]
109 #[must_use]
110 pub fn dcdc_vout_sel_aon(&mut self) -> DCDC_VOUT_SEL_AON_W<DCDC_TOP_0_SPEC> {
111 DCDC_VOUT_SEL_AON_W::new(self, 0)
112 }
113 #[doc = "Bits 8:11"]
114 #[inline(always)]
115 #[must_use]
116 pub fn dcdc_vpfm_aon(&mut self) -> DCDC_VPFM_AON_W<DCDC_TOP_0_SPEC> {
117 DCDC_VPFM_AON_W::new(self, 8)
118 }
119 #[doc = "Bit 12"]
120 #[inline(always)]
121 #[must_use]
122 pub fn dcdc_osc_2m_mode_aon(&mut self) -> DCDC_OSC_2M_MODE_AON_W<DCDC_TOP_0_SPEC> {
123 DCDC_OSC_2M_MODE_AON_W::new(self, 12)
124 }
125 #[doc = "Bits 16:19"]
126 #[inline(always)]
127 #[must_use]
128 pub fn dcdc_osc_freq_trim_aon(&mut self) -> DCDC_OSC_FREQ_TRIM_AON_W<DCDC_TOP_0_SPEC> {
129 DCDC_OSC_FREQ_TRIM_AON_W::new(self, 16)
130 }
131 #[doc = "Bits 20:24"]
132 #[inline(always)]
133 #[must_use]
134 pub fn dcdc_slope_curr_sel_aon(&mut self) -> DCDC_SLOPE_CURR_SEL_AON_W<DCDC_TOP_0_SPEC> {
135 DCDC_SLOPE_CURR_SEL_AON_W::new(self, 20)
136 }
137 #[doc = "Bit 25"]
138 #[inline(always)]
139 #[must_use]
140 pub fn dcdc_en_stop_osc_aon(&mut self) -> DCDC_EN_STOP_OSC_AON_W<DCDC_TOP_0_SPEC> {
141 DCDC_EN_STOP_OSC_AON_W::new(self, 25)
142 }
143 #[doc = "Bit 26"]
144 #[inline(always)]
145 #[must_use]
146 pub fn dcdc_en_slow_osc_aon(&mut self) -> DCDC_EN_SLOW_OSC_AON_W<DCDC_TOP_0_SPEC> {
147 DCDC_EN_SLOW_OSC_AON_W::new(self, 26)
148 }
149 #[doc = "Bit 27"]
150 #[inline(always)]
151 #[must_use]
152 pub fn dcdc_en_osc_inhibit_t2_aon(&mut self) -> DCDC_EN_OSC_INHIBIT_T2_AON_W<DCDC_TOP_0_SPEC> {
153 DCDC_EN_OSC_INHIBIT_T2_AON_W::new(self, 27)
154 }
155 #[doc = "Bits 28:29"]
156 #[inline(always)]
157 #[must_use]
158 pub fn dcdc_sstart_time_aon(&mut self) -> DCDC_SSTART_TIME_AON_W<DCDC_TOP_0_SPEC> {
159 DCDC_SSTART_TIME_AON_W::new(self, 28)
160 }
161 #[doc = "Bit 30"]
162 #[inline(always)]
163 #[must_use]
164 pub fn dcdc_dis_aon(&mut self) -> DCDC_DIS_AON_W<DCDC_TOP_0_SPEC> {
165 DCDC_DIS_AON_W::new(self, 30)
166 }
167 #[doc = "Bit 31"]
168 #[inline(always)]
169 #[must_use]
170 pub fn dcdc_rdy_aon(&mut self) -> DCDC_RDY_AON_W<DCDC_TOP_0_SPEC> {
171 DCDC_RDY_AON_W::new(self, 31)
172 }
173 #[doc = r" Writes raw bits to the register."]
174 #[doc = r""]
175 #[doc = r" # Safety"]
176 #[doc = r""]
177 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
178 #[inline(always)]
179 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
180 self.bits = bits;
181 self
182 }
183}
184#[doc = "dcdc_top_0.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcdc_top_0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcdc_top_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
185pub struct DCDC_TOP_0_SPEC;
186impl crate::RegisterSpec for DCDC_TOP_0_SPEC {
187 type Ux = u32;
188}
189#[doc = "`read()` method returns [`dcdc_top_0::R`](R) reader structure"]
190impl crate::Readable for DCDC_TOP_0_SPEC {}
191#[doc = "`write(|w| ..)` method takes [`dcdc_top_0::W`](W) writer structure"]
192impl crate::Writable for DCDC_TOP_0_SPEC {
193 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
194 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
195}
196#[doc = "`reset()` method sets dcdc_top_0 to value 0"]
197impl crate::Resettable for DCDC_TOP_0_SPEC {
198 const RESET_VALUE: Self::Ux = 0;
199}