bl61x_pac/uart/
interrupt_clear.rs

1#[doc = "Register `interrupt_clear` writer"]
2pub type W = crate::W<INTERRUPT_CLEAR_SPEC>;
3#[doc = "Field `transmit_transfer` writer - Write 1 to clear transmit transfer finish signal"]
4pub use AUTO_BAUDRATE_FIVE_FIVE_W as TRANSMIT_TRANSFER_W;
5#[doc = "Field `receive_transfer` writer - Write 1 to clear receive transfer finish signal"]
6pub use AUTO_BAUDRATE_FIVE_FIVE_W as RECEIVE_TRANSFER_W;
7#[doc = "Field `receive_timeout` writer - Write 1 to clear receive timed-out"]
8pub use AUTO_BAUDRATE_FIVE_FIVE_W as RECEIVE_TIMEOUT_W;
9#[doc = "Field `receive_parity` writer - Write 1 to clear receive parity check failure"]
10pub use AUTO_BAUDRATE_FIVE_FIVE_W as RECEIVE_PARITY_W;
11#[doc = "Field `receive_sync_error` writer - Write 1 to clear receive LIN mode synchronization field error"]
12pub use AUTO_BAUDRATE_FIVE_FIVE_W as RECEIVE_SYNC_ERROR_W;
13#[doc = "Field `receive_byte_count` writer - Write 1 to clear receive byte count reached"]
14pub use AUTO_BAUDRATE_FIVE_FIVE_W as RECEIVE_BYTE_COUNT_W;
15#[doc = "Field `auto_baudrate_start_bit` writer - Write 1 to clear receive auto baudrate detection finished using start bit"]
16pub use AUTO_BAUDRATE_FIVE_FIVE_W as AUTO_BAUDRATE_START_BIT_W;
17#[doc = "Write 1 to clear receive auto baudrate detection finished using 0x55\n\nValue on reset: 0"]
18#[derive(Clone, Copy, Debug, PartialEq, Eq)]
19pub enum INTERRUPT_CLEAR_AW {
20    #[doc = "1: Write 1 to clear interrupt state"]
21    CLEAR = 1,
22}
23impl From<INTERRUPT_CLEAR_AW> for bool {
24    #[inline(always)]
25    fn from(variant: INTERRUPT_CLEAR_AW) -> Self {
26        variant as u8 != 0
27    }
28}
29#[doc = "Field `auto_baudrate_five_five` writer - Write 1 to clear receive auto baudrate detection finished using 0x55"]
30pub type AUTO_BAUDRATE_FIVE_FIVE_W<'a, REG> = crate::BitWriter<'a, REG, INTERRUPT_CLEAR_AW>;
31impl<'a, REG> AUTO_BAUDRATE_FIVE_FIVE_W<'a, REG>
32where
33    REG: crate::Writable + crate::RegisterSpec,
34{
35    #[doc = "Write 1 to clear interrupt state"]
36    #[inline(always)]
37    pub fn clear(self) -> &'a mut crate::W<REG> {
38        self.variant(INTERRUPT_CLEAR_AW::CLEAR)
39    }
40}
41impl W {
42    #[doc = "Bit 0 - Write 1 to clear transmit transfer finish signal"]
43    #[inline(always)]
44    #[must_use]
45    pub fn transmit_transfer(&mut self) -> TRANSMIT_TRANSFER_W<INTERRUPT_CLEAR_SPEC> {
46        TRANSMIT_TRANSFER_W::new(self, 0)
47    }
48    #[doc = "Bit 1 - Write 1 to clear receive transfer finish signal"]
49    #[inline(always)]
50    #[must_use]
51    pub fn receive_transfer(&mut self) -> RECEIVE_TRANSFER_W<INTERRUPT_CLEAR_SPEC> {
52        RECEIVE_TRANSFER_W::new(self, 1)
53    }
54    #[doc = "Bit 4 - Write 1 to clear receive timed-out"]
55    #[inline(always)]
56    #[must_use]
57    pub fn receive_timeout(&mut self) -> RECEIVE_TIMEOUT_W<INTERRUPT_CLEAR_SPEC> {
58        RECEIVE_TIMEOUT_W::new(self, 4)
59    }
60    #[doc = "Bit 5 - Write 1 to clear receive parity check failure"]
61    #[inline(always)]
62    #[must_use]
63    pub fn receive_parity(&mut self) -> RECEIVE_PARITY_W<INTERRUPT_CLEAR_SPEC> {
64        RECEIVE_PARITY_W::new(self, 5)
65    }
66    #[doc = "Bit 8 - Write 1 to clear receive LIN mode synchronization field error"]
67    #[inline(always)]
68    #[must_use]
69    pub fn receive_sync_error(&mut self) -> RECEIVE_SYNC_ERROR_W<INTERRUPT_CLEAR_SPEC> {
70        RECEIVE_SYNC_ERROR_W::new(self, 8)
71    }
72    #[doc = "Bit 9 - Write 1 to clear receive byte count reached"]
73    #[inline(always)]
74    #[must_use]
75    pub fn receive_byte_count(&mut self) -> RECEIVE_BYTE_COUNT_W<INTERRUPT_CLEAR_SPEC> {
76        RECEIVE_BYTE_COUNT_W::new(self, 9)
77    }
78    #[doc = "Bit 10 - Write 1 to clear receive auto baudrate detection finished using start bit"]
79    #[inline(always)]
80    #[must_use]
81    pub fn auto_baudrate_start_bit(&mut self) -> AUTO_BAUDRATE_START_BIT_W<INTERRUPT_CLEAR_SPEC> {
82        AUTO_BAUDRATE_START_BIT_W::new(self, 10)
83    }
84    #[doc = "Bit 11 - Write 1 to clear receive auto baudrate detection finished using 0x55"]
85    #[inline(always)]
86    #[must_use]
87    pub fn auto_baudrate_five_five(&mut self) -> AUTO_BAUDRATE_FIVE_FIVE_W<INTERRUPT_CLEAR_SPEC> {
88        AUTO_BAUDRATE_FIVE_FIVE_W::new(self, 11)
89    }
90    #[doc = r" Writes raw bits to the register."]
91    #[doc = r""]
92    #[doc = r" # Safety"]
93    #[doc = r""]
94    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
95    #[inline(always)]
96    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
97        self.bits = bits;
98        self
99    }
100}
101#[doc = "Clear interrupt register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_clear::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
102pub struct INTERRUPT_CLEAR_SPEC;
103impl crate::RegisterSpec for INTERRUPT_CLEAR_SPEC {
104    type Ux = u32;
105}
106#[doc = "`write(|w| ..)` method takes [`interrupt_clear::W`](W) writer structure"]
107impl crate::Writable for INTERRUPT_CLEAR_SPEC {
108    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
109    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
110}
111#[doc = "`reset()` method sets interrupt_clear to value 0"]
112impl crate::Resettable for INTERRUPT_CLEAR_SPEC {
113    const RESET_VALUE: Self::Ux = 0;
114}
bl61x_pac/uart/interrupt_clear.rs

bl61x_pac/uart/
interrupt_clear.rs
