bl61x_pac/glb/
cgen_m.rs

1#[doc = "Register `cgen_m` reader"]
2pub type R = crate::R<CGEN_M_SPEC>;
3#[doc = "Register `cgen_m` writer"]
4pub type W = crate::W<CGEN_M_SPEC>;
5#[doc = "Field `cgen_m_cpu` reader - "]
6pub type CGEN_M_CPU_R = crate::BitReader;
7#[doc = "Field `cgen_m_cpu` writer - "]
8pub type CGEN_M_CPU_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `cgen_m_sdu` reader - "]
10pub type CGEN_M_SDU_R = crate::BitReader;
11#[doc = "Field `cgen_m_sdu` writer - "]
12pub type CGEN_M_SDU_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `cgen_m_sec` reader - "]
14pub type CGEN_M_SEC_R = crate::BitReader;
15#[doc = "Field `cgen_m_sec` writer - "]
16pub type CGEN_M_SEC_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `cgen_m_dma` reader - "]
18pub type CGEN_M_DMA_R = crate::BitReader;
19#[doc = "Field `cgen_m_dma` writer - "]
20pub type CGEN_M_DMA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `cgen_m_cci` reader - "]
22pub type CGEN_M_CCI_R = crate::BitReader;
23#[doc = "Field `cgen_m_cci` writer - "]
24pub type CGEN_M_CCI_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0"]
27    #[inline(always)]
28    pub fn cgen_m_cpu(&self) -> CGEN_M_CPU_R {
29        CGEN_M_CPU_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1"]
32    #[inline(always)]
33    pub fn cgen_m_sdu(&self) -> CGEN_M_SDU_R {
34        CGEN_M_SDU_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2"]
37    #[inline(always)]
38    pub fn cgen_m_sec(&self) -> CGEN_M_SEC_R {
39        CGEN_M_SEC_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 3"]
42    #[inline(always)]
43    pub fn cgen_m_dma(&self) -> CGEN_M_DMA_R {
44        CGEN_M_DMA_R::new(((self.bits >> 3) & 1) != 0)
45    }
46    #[doc = "Bit 4"]
47    #[inline(always)]
48    pub fn cgen_m_cci(&self) -> CGEN_M_CCI_R {
49        CGEN_M_CCI_R::new(((self.bits >> 4) & 1) != 0)
50    }
51}
52impl W {
53    #[doc = "Bit 0"]
54    #[inline(always)]
55    #[must_use]
56    pub fn cgen_m_cpu(&mut self) -> CGEN_M_CPU_W<CGEN_M_SPEC> {
57        CGEN_M_CPU_W::new(self, 0)
58    }
59    #[doc = "Bit 1"]
60    #[inline(always)]
61    #[must_use]
62    pub fn cgen_m_sdu(&mut self) -> CGEN_M_SDU_W<CGEN_M_SPEC> {
63        CGEN_M_SDU_W::new(self, 1)
64    }
65    #[doc = "Bit 2"]
66    #[inline(always)]
67    #[must_use]
68    pub fn cgen_m_sec(&mut self) -> CGEN_M_SEC_W<CGEN_M_SPEC> {
69        CGEN_M_SEC_W::new(self, 2)
70    }
71    #[doc = "Bit 3"]
72    #[inline(always)]
73    #[must_use]
74    pub fn cgen_m_dma(&mut self) -> CGEN_M_DMA_W<CGEN_M_SPEC> {
75        CGEN_M_DMA_W::new(self, 3)
76    }
77    #[doc = "Bit 4"]
78    #[inline(always)]
79    #[must_use]
80    pub fn cgen_m_cci(&mut self) -> CGEN_M_CCI_W<CGEN_M_SPEC> {
81        CGEN_M_CCI_W::new(self, 4)
82    }
83    #[doc = r" Writes raw bits to the register."]
84    #[doc = r""]
85    #[doc = r" # Safety"]
86    #[doc = r""]
87    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
88    #[inline(always)]
89    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
90        self.bits = bits;
91        self
92    }
93}
94#[doc = "cgen_m.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cgen_m::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cgen_m::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
95pub struct CGEN_M_SPEC;
96impl crate::RegisterSpec for CGEN_M_SPEC {
97    type Ux = u32;
98}
99#[doc = "`read()` method returns [`cgen_m::R`](R) reader structure"]
100impl crate::Readable for CGEN_M_SPEC {}
101#[doc = "`write(|w| ..)` method takes [`cgen_m::W`](W) writer structure"]
102impl crate::Writable for CGEN_M_SPEC {
103    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
104    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105}
106#[doc = "`reset()` method sets cgen_m to value 0"]
107impl crate::Resettable for CGEN_M_SPEC {
108    const RESET_VALUE: Self::Ux = 0;
109}
bl61x_pac/glb/cgen_m.rs

bl61x_pac/glb/
cgen_m.rs
