bl61x_pac/emac/
interrupt_source.rs

1#[doc = "Register `interrupt_source` reader"]
2pub type R = crate::R<INTERRUPT_SOURCE_SPEC>;
3#[doc = "Register `interrupt_source` writer"]
4pub type W = crate::W<INTERRUPT_SOURCE_SPEC>;
5#[doc = "Field `buffer_transmitted` reader - Buffer transmitted interrupt state"]
6pub use CONTROL_RECEIVE_R as BUFFER_TRANSMITTED_R;
7#[doc = "Field `transmit_error` reader - Transmit error interrupt state"]
8pub use CONTROL_RECEIVE_R as TRANSMIT_ERROR_R;
9#[doc = "Field `frame_received` reader - Frame received interrupt state"]
10pub use CONTROL_RECEIVE_R as FRAME_RECEIVED_R;
11#[doc = "Field `receive_error` reader - Receive error interrupt state"]
12pub use CONTROL_RECEIVE_R as RECEIVE_ERROR_R;
13#[doc = "Field `busy` reader - Lack of buffer interrupt state"]
14pub use CONTROL_RECEIVE_R as BUSY_R;
15#[doc = "Field `control_transmit` reader - Control frame transmitted interrupt state"]
16pub use CONTROL_RECEIVE_R as CONTROL_TRANSMIT_R;
17#[doc = "Field `buffer_transmitted` writer - Buffer transmitted interrupt state"]
18pub use CONTROL_RECEIVE_W as BUFFER_TRANSMITTED_W;
19#[doc = "Field `transmit_error` writer - Transmit error interrupt state"]
20pub use CONTROL_RECEIVE_W as TRANSMIT_ERROR_W;
21#[doc = "Field `frame_received` writer - Frame received interrupt state"]
22pub use CONTROL_RECEIVE_W as FRAME_RECEIVED_W;
23#[doc = "Field `receive_error` writer - Receive error interrupt state"]
24pub use CONTROL_RECEIVE_W as RECEIVE_ERROR_W;
25#[doc = "Field `busy` writer - Lack of buffer interrupt state"]
26pub use CONTROL_RECEIVE_W as BUSY_W;
27#[doc = "Field `control_transmit` writer - Control frame transmitted interrupt state"]
28pub use CONTROL_RECEIVE_W as CONTROL_TRANSMIT_W;
29#[doc = "Field `control_receive` reader - Control frame received interrupt state"]
30pub type CONTROL_RECEIVE_R = crate::BitReader<INTERRUPT_STATE_A>;
31#[doc = "Control frame received interrupt state\n\nValue on reset: 0"]
32#[derive(Clone, Copy, Debug, PartialEq, Eq)]
33pub enum INTERRUPT_STATE_A {
34    #[doc = "1: Has interrupt"]
35    HAS_INTERRUPT = 1,
36    #[doc = "0: No interrupt occurred"]
37    NO_INTERRUPT = 0,
38}
39impl From<INTERRUPT_STATE_A> for bool {
40    #[inline(always)]
41    fn from(variant: INTERRUPT_STATE_A) -> Self {
42        variant as u8 != 0
43    }
44}
45impl CONTROL_RECEIVE_R {
46    #[doc = "Get enumerated values variant"]
47    #[inline(always)]
48    pub const fn variant(&self) -> INTERRUPT_STATE_A {
49        match self.bits {
50            true => INTERRUPT_STATE_A::HAS_INTERRUPT,
51            false => INTERRUPT_STATE_A::NO_INTERRUPT,
52        }
53    }
54    #[doc = "Has interrupt"]
55    #[inline(always)]
56    pub fn is_has_interrupt(&self) -> bool {
57        *self == INTERRUPT_STATE_A::HAS_INTERRUPT
58    }
59    #[doc = "No interrupt occurred"]
60    #[inline(always)]
61    pub fn is_no_interrupt(&self) -> bool {
62        *self == INTERRUPT_STATE_A::NO_INTERRUPT
63    }
64}
65#[doc = "Field `control_receive` writer - Control frame received interrupt state"]
66pub type CONTROL_RECEIVE_W<'a, REG> = crate::BitWriter1C<'a, REG, INTERRUPT_STATE_A>;
67impl<'a, REG> CONTROL_RECEIVE_W<'a, REG>
68where
69    REG: crate::Writable + crate::RegisterSpec,
70{
71    #[doc = "Has interrupt"]
72    #[inline(always)]
73    pub fn has_interrupt(self) -> &'a mut crate::W<REG> {
74        self.variant(INTERRUPT_STATE_A::HAS_INTERRUPT)
75    }
76    #[doc = "No interrupt occurred"]
77    #[inline(always)]
78    pub fn no_interrupt(self) -> &'a mut crate::W<REG> {
79        self.variant(INTERRUPT_STATE_A::NO_INTERRUPT)
80    }
81}
82impl R {
83    #[doc = "Bit 0 - Buffer transmitted interrupt state"]
84    #[inline(always)]
85    pub fn buffer_transmitted(&self) -> BUFFER_TRANSMITTED_R {
86        BUFFER_TRANSMITTED_R::new((self.bits & 1) != 0)
87    }
88    #[doc = "Bit 1 - Transmit error interrupt state"]
89    #[inline(always)]
90    pub fn transmit_error(&self) -> TRANSMIT_ERROR_R {
91        TRANSMIT_ERROR_R::new(((self.bits >> 1) & 1) != 0)
92    }
93    #[doc = "Bit 2 - Frame received interrupt state"]
94    #[inline(always)]
95    pub fn frame_received(&self) -> FRAME_RECEIVED_R {
96        FRAME_RECEIVED_R::new(((self.bits >> 2) & 1) != 0)
97    }
98    #[doc = "Bit 3 - Receive error interrupt state"]
99    #[inline(always)]
100    pub fn receive_error(&self) -> RECEIVE_ERROR_R {
101        RECEIVE_ERROR_R::new(((self.bits >> 3) & 1) != 0)
102    }
103    #[doc = "Bit 4 - Lack of buffer interrupt state"]
104    #[inline(always)]
105    pub fn busy(&self) -> BUSY_R {
106        BUSY_R::new(((self.bits >> 4) & 1) != 0)
107    }
108    #[doc = "Bit 5 - Control frame transmitted interrupt state"]
109    #[inline(always)]
110    pub fn control_transmit(&self) -> CONTROL_TRANSMIT_R {
111        CONTROL_TRANSMIT_R::new(((self.bits >> 5) & 1) != 0)
112    }
113    #[doc = "Bit 6 - Control frame received interrupt state"]
114    #[inline(always)]
115    pub fn control_receive(&self) -> CONTROL_RECEIVE_R {
116        CONTROL_RECEIVE_R::new(((self.bits >> 6) & 1) != 0)
117    }
118}
119impl W {
120    #[doc = "Bit 0 - Buffer transmitted interrupt state"]
121    #[inline(always)]
122    #[must_use]
123    pub fn buffer_transmitted(&mut self) -> BUFFER_TRANSMITTED_W<INTERRUPT_SOURCE_SPEC> {
124        BUFFER_TRANSMITTED_W::new(self, 0)
125    }
126    #[doc = "Bit 1 - Transmit error interrupt state"]
127    #[inline(always)]
128    #[must_use]
129    pub fn transmit_error(&mut self) -> TRANSMIT_ERROR_W<INTERRUPT_SOURCE_SPEC> {
130        TRANSMIT_ERROR_W::new(self, 1)
131    }
132    #[doc = "Bit 2 - Frame received interrupt state"]
133    #[inline(always)]
134    #[must_use]
135    pub fn frame_received(&mut self) -> FRAME_RECEIVED_W<INTERRUPT_SOURCE_SPEC> {
136        FRAME_RECEIVED_W::new(self, 2)
137    }
138    #[doc = "Bit 3 - Receive error interrupt state"]
139    #[inline(always)]
140    #[must_use]
141    pub fn receive_error(&mut self) -> RECEIVE_ERROR_W<INTERRUPT_SOURCE_SPEC> {
142        RECEIVE_ERROR_W::new(self, 3)
143    }
144    #[doc = "Bit 4 - Lack of buffer interrupt state"]
145    #[inline(always)]
146    #[must_use]
147    pub fn busy(&mut self) -> BUSY_W<INTERRUPT_SOURCE_SPEC> {
148        BUSY_W::new(self, 4)
149    }
150    #[doc = "Bit 5 - Control frame transmitted interrupt state"]
151    #[inline(always)]
152    #[must_use]
153    pub fn control_transmit(&mut self) -> CONTROL_TRANSMIT_W<INTERRUPT_SOURCE_SPEC> {
154        CONTROL_TRANSMIT_W::new(self, 5)
155    }
156    #[doc = "Bit 6 - Control frame received interrupt state"]
157    #[inline(always)]
158    #[must_use]
159    pub fn control_receive(&mut self) -> CONTROL_RECEIVE_W<INTERRUPT_SOURCE_SPEC> {
160        CONTROL_RECEIVE_W::new(self, 6)
161    }
162    #[doc = r" Writes raw bits to the register."]
163    #[doc = r""]
164    #[doc = r" # Safety"]
165    #[doc = r""]
166    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
167    #[inline(always)]
168    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
169        self.bits = bits;
170        self
171    }
172}
173#[doc = "Interrupt source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_source::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_source::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
174pub struct INTERRUPT_SOURCE_SPEC;
175impl crate::RegisterSpec for INTERRUPT_SOURCE_SPEC {
176    type Ux = u32;
177}
178#[doc = "`read()` method returns [`interrupt_source::R`](R) reader structure"]
179impl crate::Readable for INTERRUPT_SOURCE_SPEC {}
180#[doc = "`write(|w| ..)` method takes [`interrupt_source::W`](W) writer structure"]
181impl crate::Writable for INTERRUPT_SOURCE_SPEC {
182    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
183    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x7f;
184}
185#[doc = "`reset()` method sets interrupt_source to value 0"]
186impl crate::Resettable for INTERRUPT_SOURCE_SPEC {
187    const RESET_VALUE: Self::Ux = 0;
188}
bl61x_pac/emac/interrupt_source.rs

bl61x_pac/emac/
interrupt_source.rs
