1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 mode: MODE,
5 interrupt_source: INTERRUPT_SOURCE,
6 interrupt_mask: INTERRUPT_MASK,
7 backed_gap: BACKED_GAP,
8 non_backed_gap_1: NON_BACKED_GAP_1,
9 non_backed_gap_2: NON_BACKED_GAP_2,
10 frame_length: FRAME_LENGTH,
11 collision: COLLISION,
12 transmit_buffer: TRANSMIT_BUFFER,
13 flow_control: FLOW_CONTROL,
14 mii_mode: MII_MODE,
15 mii_command: MII_COMMAND,
16 mii_address: MII_ADDRESS,
17 control_write: CONTROL_WRITE,
18 control_read: CONTROL_READ,
19 mii_state: MII_STATE,
20 mac_address: [MAC_ADDRESS; 2],
21 hash: [HASH; 2],
22 transmit_control: TRANSMIT_CONTROL,
23}
24impl RegisterBlock {
25 #[doc = "0x00 - Interface enables and configurations"]
26 #[inline(always)]
27 pub const fn mode(&self) -> &MODE {
28 &self.mode
29 }
30 #[doc = "0x04 - Interrupt source register"]
31 #[inline(always)]
32 pub const fn interrupt_source(&self) -> &INTERRUPT_SOURCE {
33 &self.interrupt_source
34 }
35 #[doc = "0x08 - Interrupt mask register"]
36 #[inline(always)]
37 pub const fn interrupt_mask(&self) -> &INTERRUPT_MASK {
38 &self.interrupt_mask
39 }
40 #[doc = "0x0c - Back-to-back inter-packet gap register"]
41 #[inline(always)]
42 pub const fn backed_gap(&self) -> &BACKED_GAP {
43 &self.backed_gap
44 }
45 #[doc = "0x10 - Non back-to-back inter-packet gap register 1"]
46 #[inline(always)]
47 pub const fn non_backed_gap_1(&self) -> &NON_BACKED_GAP_1 {
48 &self.non_backed_gap_1
49 }
50 #[doc = "0x14 - Non back-to-back inter-packet gap register 2"]
51 #[inline(always)]
52 pub const fn non_backed_gap_2(&self) -> &NON_BACKED_GAP_2 {
53 &self.non_backed_gap_2
54 }
55 #[doc = "0x18 - Minimum and maximum ethernet frame length"]
56 #[inline(always)]
57 pub const fn frame_length(&self) -> &FRAME_LENGTH {
58 &self.frame_length
59 }
60 #[doc = "0x1c - Collision time window and maximum retries"]
61 #[inline(always)]
62 pub const fn collision(&self) -> &COLLISION {
63 &self.collision
64 }
65 #[doc = "0x20 - Transmit buffer descriptor"]
66 #[inline(always)]
67 pub const fn transmit_buffer(&self) -> &TRANSMIT_BUFFER {
68 &self.transmit_buffer
69 }
70 #[doc = "0x24 - Control frame function register"]
71 #[inline(always)]
72 pub const fn flow_control(&self) -> &FLOW_CONTROL {
73 &self.flow_control
74 }
75 #[doc = "0x28 - MII clock divider and premable enable"]
76 #[inline(always)]
77 pub const fn mii_mode(&self) -> &MII_MODE {
78 &self.mii_mode
79 }
80 #[doc = "0x2c - MII control data, read and scan state"]
81 #[inline(always)]
82 pub const fn mii_command(&self) -> &MII_COMMAND {
83 &self.mii_command
84 }
85 #[doc = "0x30 - Physical layer bus address"]
86 #[inline(always)]
87 pub const fn mii_address(&self) -> &MII_ADDRESS {
88 &self.mii_address
89 }
90 #[doc = "0x34 - Write data to MII physcial layer"]
91 #[inline(always)]
92 pub const fn control_write(&self) -> &CONTROL_WRITE {
93 &self.control_write
94 }
95 #[doc = "0x38 - Read data from MII physcial layer"]
96 #[inline(always)]
97 pub const fn control_read(&self) -> &CONTROL_READ {
98 &self.control_read
99 }
100 #[doc = "0x3c - MII bus and link layer state"]
101 #[inline(always)]
102 pub const fn mii_state(&self) -> &MII_STATE {
103 &self.mii_state
104 }
105 #[doc = "0x40..0x48 - Media Access Control address"]
106 #[inline(always)]
107 pub const fn mac_address(&self, n: usize) -> &MAC_ADDRESS {
108 &self.mac_address[n]
109 }
110 #[doc = "Iterator for array of:"]
111 #[doc = "0x40..0x48 - Media Access Control address"]
112 #[inline(always)]
113 pub fn mac_address_iter(&self) -> impl Iterator<Item = &MAC_ADDRESS> {
114 self.mac_address.iter()
115 }
116 #[doc = "0x48..0x50 - Hash register"]
117 #[inline(always)]
118 pub const fn hash(&self, n: usize) -> &HASH {
119 &self.hash[n]
120 }
121 #[doc = "Iterator for array of:"]
122 #[doc = "0x48..0x50 - Hash register"]
123 #[inline(always)]
124 pub fn hash_iter(&self) -> impl Iterator<Item = &HASH> {
125 self.hash.iter()
126 }
127 #[doc = "0x50 - Transmit control register"]
128 #[inline(always)]
129 pub const fn transmit_control(&self) -> &TRANSMIT_CONTROL {
130 &self.transmit_control
131 }
132}
133#[doc = "mode (rw) register accessor: Interface enables and configurations\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mode`]
134module"]
135pub type MODE = crate::Reg<mode::MODE_SPEC>;
136#[doc = "Interface enables and configurations"]
137pub mod mode;
138#[doc = "interrupt_source (rw) register accessor: Interrupt source register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_source::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_source::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_source`]
139module"]
140pub type INTERRUPT_SOURCE = crate::Reg<interrupt_source::INTERRUPT_SOURCE_SPEC>;
141#[doc = "Interrupt source register"]
142pub mod interrupt_source;
143#[doc = "interrupt_mask (rw) register accessor: Interrupt mask register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`interrupt_mask::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`interrupt_mask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@interrupt_mask`]
144module"]
145pub type INTERRUPT_MASK = crate::Reg<interrupt_mask::INTERRUPT_MASK_SPEC>;
146#[doc = "Interrupt mask register"]
147pub mod interrupt_mask;
148#[doc = "backed_gap (rw) register accessor: Back-to-back inter-packet gap register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`backed_gap::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`backed_gap::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@backed_gap`]
149module"]
150pub type BACKED_GAP = crate::Reg<backed_gap::BACKED_GAP_SPEC>;
151#[doc = "Back-to-back inter-packet gap register"]
152pub mod backed_gap;
153#[doc = "non_backed_gap_1 (rw) register accessor: Non back-to-back inter-packet gap register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`non_backed_gap_1::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`non_backed_gap_1::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@non_backed_gap_1`]
154module"]
155pub type NON_BACKED_GAP_1 = crate::Reg<non_backed_gap_1::NON_BACKED_GAP_1_SPEC>;
156#[doc = "Non back-to-back inter-packet gap register 1"]
157pub mod non_backed_gap_1;
158#[doc = "non_backed_gap_2 (rw) register accessor: Non back-to-back inter-packet gap register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`non_backed_gap_2::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`non_backed_gap_2::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@non_backed_gap_2`]
159module"]
160pub type NON_BACKED_GAP_2 = crate::Reg<non_backed_gap_2::NON_BACKED_GAP_2_SPEC>;
161#[doc = "Non back-to-back inter-packet gap register 2"]
162pub mod non_backed_gap_2;
163#[doc = "frame_length (rw) register accessor: Minimum and maximum ethernet frame length\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`frame_length::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`frame_length::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@frame_length`]
164module"]
165pub type FRAME_LENGTH = crate::Reg<frame_length::FRAME_LENGTH_SPEC>;
166#[doc = "Minimum and maximum ethernet frame length"]
167pub mod frame_length;
168#[doc = "collision (rw) register accessor: Collision time window and maximum retries\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`collision::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`collision::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@collision`]
169module"]
170pub type COLLISION = crate::Reg<collision::COLLISION_SPEC>;
171#[doc = "Collision time window and maximum retries"]
172pub mod collision;
173#[doc = "transmit_buffer (rw) register accessor: Transmit buffer descriptor\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`transmit_buffer::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`transmit_buffer::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@transmit_buffer`]
174module"]
175pub type TRANSMIT_BUFFER = crate::Reg<transmit_buffer::TRANSMIT_BUFFER_SPEC>;
176#[doc = "Transmit buffer descriptor"]
177pub mod transmit_buffer;
178#[doc = "flow_control (rw) register accessor: Control frame function register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flow_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flow_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@flow_control`]
179module"]
180pub type FLOW_CONTROL = crate::Reg<flow_control::FLOW_CONTROL_SPEC>;
181#[doc = "Control frame function register"]
182pub mod flow_control;
183#[doc = "mii_mode (rw) register accessor: MII clock divider and premable enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mii_mode::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mii_mode::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mii_mode`]
184module"]
185pub type MII_MODE = crate::Reg<mii_mode::MII_MODE_SPEC>;
186#[doc = "MII clock divider and premable enable"]
187pub mod mii_mode;
188#[doc = "mii_command (rw) register accessor: MII control data, read and scan state\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mii_command::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mii_command::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mii_command`]
189module"]
190pub type MII_COMMAND = crate::Reg<mii_command::MII_COMMAND_SPEC>;
191#[doc = "MII control data, read and scan state"]
192pub mod mii_command;
193#[doc = "mii_address (rw) register accessor: Physical layer bus address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mii_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mii_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mii_address`]
194module"]
195pub type MII_ADDRESS = crate::Reg<mii_address::MII_ADDRESS_SPEC>;
196#[doc = "Physical layer bus address"]
197pub mod mii_address;
198#[doc = "control_write (rw) register accessor: Write data to MII physcial layer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control_write::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control_write::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_write`]
199module"]
200pub type CONTROL_WRITE = crate::Reg<control_write::CONTROL_WRITE_SPEC>;
201#[doc = "Write data to MII physcial layer"]
202pub mod control_write;
203#[doc = "control_read (rw) register accessor: Read data from MII physcial layer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`control_read::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`control_read::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@control_read`]
204module"]
205pub type CONTROL_READ = crate::Reg<control_read::CONTROL_READ_SPEC>;
206#[doc = "Read data from MII physcial layer"]
207pub mod control_read;
208#[doc = "mii_state (rw) register accessor: MII bus and link layer state\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mii_state::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mii_state::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mii_state`]
209module"]
210pub type MII_STATE = crate::Reg<mii_state::MII_STATE_SPEC>;
211#[doc = "MII bus and link layer state"]
212pub mod mii_state;
213#[doc = "mac_address (rw) register accessor: Media Access Control address\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`mac_address::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`mac_address::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mac_address`]
214module"]
215pub type MAC_ADDRESS = crate::Reg<mac_address::MAC_ADDRESS_SPEC>;
216#[doc = "Media Access Control address"]
217pub mod mac_address;
218#[doc = "hash (rw) register accessor: Hash register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`hash::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`hash::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@hash`]
219module"]
220pub type HASH = crate::Reg<hash::HASH_SPEC>;
221#[doc = "Hash register"]
222pub mod hash;
223#[doc = "transmit_control (rw) register accessor: Transmit control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`transmit_control::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`transmit_control::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@transmit_control`]
224module"]
225pub type TRANSMIT_CONTROL = crate::Reg<transmit_control::TRANSMIT_CONTROL_SPEC>;
226#[doc = "Transmit control register"]
227pub mod transmit_control;