bl616_pac/glb/
uart_config.rs

1#[doc = "Register `uart_config` reader"]
2pub struct R(crate::R<UART_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_config` writer"]
17pub struct W(crate::W<UART_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `clock_divide` reader - Peripheral clock divide factor"]
38pub type CLOCK_DIVIDE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `clock_divide` writer - Peripheral clock divide factor"]
40pub type CLOCK_DIVIDE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, UART_CONFIG_SPEC, u8, u8, 3, O>;
42#[doc = "Field `clock_enable` reader - Peripheral level clock gate enable"]
43pub type CLOCK_ENABLE_R = crate::BitReader<bool>;
44#[doc = "Field `clock_enable` writer - Peripheral level clock gate enable"]
45pub type CLOCK_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_CONFIG_SPEC, bool, O>;
46#[doc = "Field `hibernate_clock_source` reader - Reads clock source from hibernate registers"]
47pub type HIBERNATE_CLOCK_SOURCE_R = crate::BitReader<bool>;
48#[doc = "Field `hibernate_clock_source_2` reader - Reads clock source from hibernate registers"]
49pub type HIBERNATE_CLOCK_SOURCE_2_R = crate::BitReader<bool>;
50impl R {
51    #[doc = "Bits 0:2 - Peripheral clock divide factor"]
52    #[inline(always)]
53    pub fn clock_divide(&self) -> CLOCK_DIVIDE_R {
54        CLOCK_DIVIDE_R::new((self.bits & 7) as u8)
55    }
56    #[doc = "Bit 4 - Peripheral level clock gate enable"]
57    #[inline(always)]
58    pub fn clock_enable(&self) -> CLOCK_ENABLE_R {
59        CLOCK_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
60    }
61    #[doc = "Bit 7 - Reads clock source from hibernate registers"]
62    #[inline(always)]
63    pub fn hibernate_clock_source(&self) -> HIBERNATE_CLOCK_SOURCE_R {
64        HIBERNATE_CLOCK_SOURCE_R::new(((self.bits >> 7) & 1) != 0)
65    }
66    #[doc = "Bit 22 - Reads clock source from hibernate registers"]
67    #[inline(always)]
68    pub fn hibernate_clock_source_2(&self) -> HIBERNATE_CLOCK_SOURCE_2_R {
69        HIBERNATE_CLOCK_SOURCE_2_R::new(((self.bits >> 22) & 1) != 0)
70    }
71}
72impl W {
73    #[doc = "Bits 0:2 - Peripheral clock divide factor"]
74    #[inline(always)]
75    #[must_use]
76    pub fn clock_divide(&mut self) -> CLOCK_DIVIDE_W<0> {
77        CLOCK_DIVIDE_W::new(self)
78    }
79    #[doc = "Bit 4 - Peripheral level clock gate enable"]
80    #[inline(always)]
81    #[must_use]
82    pub fn clock_enable(&mut self) -> CLOCK_ENABLE_W<4> {
83        CLOCK_ENABLE_W::new(self)
84    }
85    #[doc = "Writes raw bits to the register."]
86    #[inline(always)]
87    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
88        self.0.bits(bits);
89        self
90    }
91}
92#[doc = "Universal Asynchronous Receiver/Transmitter configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_config](index.html) module"]
93pub struct UART_CONFIG_SPEC;
94impl crate::RegisterSpec for UART_CONFIG_SPEC {
95    type Ux = u32;
96}
97#[doc = "`read()` method returns [uart_config::R](R) reader structure"]
98impl crate::Readable for UART_CONFIG_SPEC {
99    type Reader = R;
100}
101#[doc = "`write(|w| ..)` method takes [uart_config::W](W) writer structure"]
102impl crate::Writable for UART_CONFIG_SPEC {
103    type Writer = W;
104    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
106}
107#[doc = "`reset()` method sets uart_config to value 0"]
108impl crate::Resettable for UART_CONFIG_SPEC {
109    const RESET_VALUE: Self::Ux = 0;
110}
bl616_pac/glb/uart_config.rs

bl616_pac/glb/
uart_config.rs
