bl616_pac/glb/
spi_config.rs

1#[doc = "Register `spi_config` reader"]
2pub struct R(crate::R<SPI_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPI_CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPI_CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPI_CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `spi_config` writer"]
17pub struct W(crate::W<SPI_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPI_CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPI_CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPI_CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `clock_divide` reader - Peripheral clock divide factor"]
38pub type CLOCK_DIVIDE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `clock_divide` writer - Peripheral clock divide factor"]
40pub type CLOCK_DIVIDE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, SPI_CONFIG_SPEC, u8, u8, 5, O>;
42#[doc = "Field `clock_enable` reader - Peripheral level clock gate enable"]
43pub type CLOCK_ENABLE_R = crate::BitReader<bool>;
44#[doc = "Field `clock_enable` writer - Peripheral level clock gate enable"]
45pub type CLOCK_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SPI_CONFIG_SPEC, bool, O>;
46#[doc = "Field `clock_source` reader - Peripheral clock source register"]
47pub type CLOCK_SOURCE_R = crate::BitReader<bool>;
48#[doc = "Field `clock_source` writer - Peripheral clock source register"]
49pub type CLOCK_SOURCE_W<'a, const O: u8> = crate::BitWriter<'a, u32, SPI_CONFIG_SPEC, bool, O>;
50#[doc = "Field `pin_swap` reader - Swap Serial Peripheral Interface pin signals"]
51pub type PIN_SWAP_R = crate::FieldReader<u8, u8>;
52#[doc = "Field `pin_swap` writer - Swap Serial Peripheral Interface pin signals"]
53pub type PIN_SWAP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SPI_CONFIG_SPEC, u8, u8, 4, O>;
54impl R {
55    #[doc = "Bits 0:4 - Peripheral clock divide factor"]
56    #[inline(always)]
57    pub fn clock_divide(&self) -> CLOCK_DIVIDE_R {
58        CLOCK_DIVIDE_R::new((self.bits & 0x1f) as u8)
59    }
60    #[doc = "Bit 8 - Peripheral level clock gate enable"]
61    #[inline(always)]
62    pub fn clock_enable(&self) -> CLOCK_ENABLE_R {
63        CLOCK_ENABLE_R::new(((self.bits >> 8) & 1) != 0)
64    }
65    #[doc = "Bit 9 - Peripheral clock source register"]
66    #[inline(always)]
67    pub fn clock_source(&self) -> CLOCK_SOURCE_R {
68        CLOCK_SOURCE_R::new(((self.bits >> 9) & 1) != 0)
69    }
70    #[doc = "Bits 16:19 - Swap Serial Peripheral Interface pin signals"]
71    #[inline(always)]
72    pub fn pin_swap(&self) -> PIN_SWAP_R {
73        PIN_SWAP_R::new(((self.bits >> 16) & 0x0f) as u8)
74    }
75}
76impl W {
77    #[doc = "Bits 0:4 - Peripheral clock divide factor"]
78    #[inline(always)]
79    #[must_use]
80    pub fn clock_divide(&mut self) -> CLOCK_DIVIDE_W<0> {
81        CLOCK_DIVIDE_W::new(self)
82    }
83    #[doc = "Bit 8 - Peripheral level clock gate enable"]
84    #[inline(always)]
85    #[must_use]
86    pub fn clock_enable(&mut self) -> CLOCK_ENABLE_W<8> {
87        CLOCK_ENABLE_W::new(self)
88    }
89    #[doc = "Bit 9 - Peripheral clock source register"]
90    #[inline(always)]
91    #[must_use]
92    pub fn clock_source(&mut self) -> CLOCK_SOURCE_W<9> {
93        CLOCK_SOURCE_W::new(self)
94    }
95    #[doc = "Bits 16:19 - Swap Serial Peripheral Interface pin signals"]
96    #[inline(always)]
97    #[must_use]
98    pub fn pin_swap(&mut self) -> PIN_SWAP_W<16> {
99        PIN_SWAP_W::new(self)
100    }
101    #[doc = "Writes raw bits to the register."]
102    #[inline(always)]
103    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
104        self.0.bits(bits);
105        self
106    }
107}
108#[doc = "Serial Peripheral Interface configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spi_config](index.html) module"]
109pub struct SPI_CONFIG_SPEC;
110impl crate::RegisterSpec for SPI_CONFIG_SPEC {
111    type Ux = u32;
112}
113#[doc = "`read()` method returns [spi_config::R](R) reader structure"]
114impl crate::Readable for SPI_CONFIG_SPEC {
115    type Reader = R;
116}
117#[doc = "`write(|w| ..)` method takes [spi_config::W](W) writer structure"]
118impl crate::Writable for SPI_CONFIG_SPEC {
119    type Writer = W;
120    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
121    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
122}
123#[doc = "`reset()` method sets spi_config to value 0"]
124impl crate::Resettable for SPI_CONFIG_SPEC {
125    const RESET_VALUE: Self::Ux = 0;
126}
bl616_pac/glb/spi_config.rs

bl616_pac/glb/
spi_config.rs
