bl616_pac/emac/
interrupt_source.rs

1#[doc = "Register `interrupt_source` reader"]
2pub struct R(crate::R<INTERRUPT_SOURCE_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTERRUPT_SOURCE_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTERRUPT_SOURCE_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTERRUPT_SOURCE_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `interrupt_source` writer"]
17pub struct W(crate::W<INTERRUPT_SOURCE_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTERRUPT_SOURCE_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTERRUPT_SOURCE_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTERRUPT_SOURCE_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `buffer_transmitted` reader - Buffer transmitted interrupt state"]
38pub use CONTROL_RECEIVE_R as BUFFER_TRANSMITTED_R;
39#[doc = "Field `transmit_error` reader - Transmit error interrupt state"]
40pub use CONTROL_RECEIVE_R as TRANSMIT_ERROR_R;
41#[doc = "Field `frame_received` reader - Frame received interrupt state"]
42pub use CONTROL_RECEIVE_R as FRAME_RECEIVED_R;
43#[doc = "Field `receive_error` reader - Receive error interrupt state"]
44pub use CONTROL_RECEIVE_R as RECEIVE_ERROR_R;
45#[doc = "Field `busy` reader - Lack of buffer interrupt state"]
46pub use CONTROL_RECEIVE_R as BUSY_R;
47#[doc = "Field `control_transmit` reader - Control frame transmitted interrupt state"]
48pub use CONTROL_RECEIVE_R as CONTROL_TRANSMIT_R;
49#[doc = "Field `buffer_transmitted` writer - Buffer transmitted interrupt state"]
50pub use CONTROL_RECEIVE_W as BUFFER_TRANSMITTED_W;
51#[doc = "Field `transmit_error` writer - Transmit error interrupt state"]
52pub use CONTROL_RECEIVE_W as TRANSMIT_ERROR_W;
53#[doc = "Field `frame_received` writer - Frame received interrupt state"]
54pub use CONTROL_RECEIVE_W as FRAME_RECEIVED_W;
55#[doc = "Field `receive_error` writer - Receive error interrupt state"]
56pub use CONTROL_RECEIVE_W as RECEIVE_ERROR_W;
57#[doc = "Field `busy` writer - Lack of buffer interrupt state"]
58pub use CONTROL_RECEIVE_W as BUSY_W;
59#[doc = "Field `control_transmit` writer - Control frame transmitted interrupt state"]
60pub use CONTROL_RECEIVE_W as CONTROL_TRANSMIT_W;
61#[doc = "Field `control_receive` reader - Control frame received interrupt state"]
62pub type CONTROL_RECEIVE_R = crate::BitReader<INTERRUPT_STATE_A>;
63#[doc = "Control frame received interrupt state\n\nValue on reset: 0"]
64#[derive(Clone, Copy, Debug, PartialEq, Eq)]
65pub enum INTERRUPT_STATE_A {
66    #[doc = "1: Has interrupt"]
67    HAS_INTERRUPT = 1,
68    #[doc = "0: No interrupt occurred"]
69    NO_INTERRUPT = 0,
70}
71impl From<INTERRUPT_STATE_A> for bool {
72    #[inline(always)]
73    fn from(variant: INTERRUPT_STATE_A) -> Self {
74        variant as u8 != 0
75    }
76}
77impl CONTROL_RECEIVE_R {
78    #[doc = "Get enumerated values variant"]
79    #[inline(always)]
80    pub fn variant(&self) -> INTERRUPT_STATE_A {
81        match self.bits {
82            true => INTERRUPT_STATE_A::HAS_INTERRUPT,
83            false => INTERRUPT_STATE_A::NO_INTERRUPT,
84        }
85    }
86    #[doc = "Checks if the value of the field is `HAS_INTERRUPT`"]
87    #[inline(always)]
88    pub fn is_has_interrupt(&self) -> bool {
89        *self == INTERRUPT_STATE_A::HAS_INTERRUPT
90    }
91    #[doc = "Checks if the value of the field is `NO_INTERRUPT`"]
92    #[inline(always)]
93    pub fn is_no_interrupt(&self) -> bool {
94        *self == INTERRUPT_STATE_A::NO_INTERRUPT
95    }
96}
97#[doc = "Field `control_receive` writer - Control frame received interrupt state"]
98pub type CONTROL_RECEIVE_W<'a, const O: u8> =
99    crate::BitWriter1C<'a, u32, INTERRUPT_SOURCE_SPEC, INTERRUPT_STATE_A, O>;
100impl<'a, const O: u8> CONTROL_RECEIVE_W<'a, O> {
101    #[doc = "Has interrupt"]
102    #[inline(always)]
103    pub fn has_interrupt(self) -> &'a mut W {
104        self.variant(INTERRUPT_STATE_A::HAS_INTERRUPT)
105    }
106    #[doc = "No interrupt occurred"]
107    #[inline(always)]
108    pub fn no_interrupt(self) -> &'a mut W {
109        self.variant(INTERRUPT_STATE_A::NO_INTERRUPT)
110    }
111}
112impl R {
113    #[doc = "Bit 0 - Buffer transmitted interrupt state"]
114    #[inline(always)]
115    pub fn buffer_transmitted(&self) -> BUFFER_TRANSMITTED_R {
116        BUFFER_TRANSMITTED_R::new((self.bits & 1) != 0)
117    }
118    #[doc = "Bit 1 - Transmit error interrupt state"]
119    #[inline(always)]
120    pub fn transmit_error(&self) -> TRANSMIT_ERROR_R {
121        TRANSMIT_ERROR_R::new(((self.bits >> 1) & 1) != 0)
122    }
123    #[doc = "Bit 2 - Frame received interrupt state"]
124    #[inline(always)]
125    pub fn frame_received(&self) -> FRAME_RECEIVED_R {
126        FRAME_RECEIVED_R::new(((self.bits >> 2) & 1) != 0)
127    }
128    #[doc = "Bit 3 - Receive error interrupt state"]
129    #[inline(always)]
130    pub fn receive_error(&self) -> RECEIVE_ERROR_R {
131        RECEIVE_ERROR_R::new(((self.bits >> 3) & 1) != 0)
132    }
133    #[doc = "Bit 4 - Lack of buffer interrupt state"]
134    #[inline(always)]
135    pub fn busy(&self) -> BUSY_R {
136        BUSY_R::new(((self.bits >> 4) & 1) != 0)
137    }
138    #[doc = "Bit 5 - Control frame transmitted interrupt state"]
139    #[inline(always)]
140    pub fn control_transmit(&self) -> CONTROL_TRANSMIT_R {
141        CONTROL_TRANSMIT_R::new(((self.bits >> 5) & 1) != 0)
142    }
143    #[doc = "Bit 6 - Control frame received interrupt state"]
144    #[inline(always)]
145    pub fn control_receive(&self) -> CONTROL_RECEIVE_R {
146        CONTROL_RECEIVE_R::new(((self.bits >> 6) & 1) != 0)
147    }
148}
149impl W {
150    #[doc = "Bit 0 - Buffer transmitted interrupt state"]
151    #[inline(always)]
152    #[must_use]
153    pub fn buffer_transmitted(&mut self) -> BUFFER_TRANSMITTED_W<0> {
154        BUFFER_TRANSMITTED_W::new(self)
155    }
156    #[doc = "Bit 1 - Transmit error interrupt state"]
157    #[inline(always)]
158    #[must_use]
159    pub fn transmit_error(&mut self) -> TRANSMIT_ERROR_W<1> {
160        TRANSMIT_ERROR_W::new(self)
161    }
162    #[doc = "Bit 2 - Frame received interrupt state"]
163    #[inline(always)]
164    #[must_use]
165    pub fn frame_received(&mut self) -> FRAME_RECEIVED_W<2> {
166        FRAME_RECEIVED_W::new(self)
167    }
168    #[doc = "Bit 3 - Receive error interrupt state"]
169    #[inline(always)]
170    #[must_use]
171    pub fn receive_error(&mut self) -> RECEIVE_ERROR_W<3> {
172        RECEIVE_ERROR_W::new(self)
173    }
174    #[doc = "Bit 4 - Lack of buffer interrupt state"]
175    #[inline(always)]
176    #[must_use]
177    pub fn busy(&mut self) -> BUSY_W<4> {
178        BUSY_W::new(self)
179    }
180    #[doc = "Bit 5 - Control frame transmitted interrupt state"]
181    #[inline(always)]
182    #[must_use]
183    pub fn control_transmit(&mut self) -> CONTROL_TRANSMIT_W<5> {
184        CONTROL_TRANSMIT_W::new(self)
185    }
186    #[doc = "Bit 6 - Control frame received interrupt state"]
187    #[inline(always)]
188    #[must_use]
189    pub fn control_receive(&mut self) -> CONTROL_RECEIVE_W<6> {
190        CONTROL_RECEIVE_W::new(self)
191    }
192    #[doc = "Writes raw bits to the register."]
193    #[inline(always)]
194    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
195        self.0.bits(bits);
196        self
197    }
198}
199#[doc = "Interrupt source register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_source](index.html) module"]
200pub struct INTERRUPT_SOURCE_SPEC;
201impl crate::RegisterSpec for INTERRUPT_SOURCE_SPEC {
202    type Ux = u32;
203}
204#[doc = "`read()` method returns [interrupt_source::R](R) reader structure"]
205impl crate::Readable for INTERRUPT_SOURCE_SPEC {
206    type Reader = R;
207}
208#[doc = "`write(|w| ..)` method takes [interrupt_source::W](W) writer structure"]
209impl crate::Writable for INTERRUPT_SOURCE_SPEC {
210    type Writer = W;
211    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
212    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x7f;
213}
214#[doc = "`reset()` method sets interrupt_source to value 0"]
215impl crate::Resettable for INTERRUPT_SOURCE_SPEC {
216    const RESET_VALUE: Self::Ux = 0;
217}
bl616_pac/emac/interrupt_source.rs

bl616_pac/emac/
interrupt_source.rs
