bl616_pac/dma/channel/
config.rs1#[doc = "Register `config` reader"]
2pub struct R(crate::R<CONFIG_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<CONFIG_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<CONFIG_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `config` writer"]
17pub struct W(crate::W<CONFIG_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<CONFIG_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<CONFIG_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `function` reader - Enable or disable DMA channel"]
38pub type FUNCTION_R = crate::BitReader<bool>;
39#[doc = "Field `function` writer - Enable or disable DMA channel"]
40pub type FUNCTION_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>;
41#[doc = "Field `source_peripheral` reader - Set source peripheral for this DMA channel"]
42pub type SOURCE_PERIPHERAL_R = crate::FieldReader<u8, u8>;
43#[doc = "Field `source_peripheral` writer - Set source peripheral for this DMA channel"]
44pub type SOURCE_PERIPHERAL_W<'a, const O: u8> =
45 crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 5, O>;
46#[doc = "Field `destination_peripheral` reader - Set destination peripheral for this DMA channel"]
47pub type DESTINATION_PERIPHERAL_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `destination_peripheral` writer - Set destination peripheral for this DMA channel"]
49pub type DESTINATION_PERIPHERAL_W<'a, const O: u8> =
50 crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 5, O>;
51#[doc = "Field `flow_control` reader - Set data direction for this channel"]
52pub type FLOW_CONTROL_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `flow_control` writer - Set data direction for this channel"]
54pub type FLOW_CONTROL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, u8, 3, O>;
55#[doc = "Field `error_mask` reader - Mask error interrupt"]
56pub type ERROR_MASK_R = crate::BitReader<bool>;
57#[doc = "Field `error_mask` writer - Mask error interrupt"]
58pub type ERROR_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>;
59#[doc = "Field `terminate_mask` reader - Mask terminal count interrupt"]
60pub type TERMINATE_MASK_R = crate::BitReader<bool>;
61#[doc = "Field `terminate_mask` writer - Mask terminal count interrupt"]
62pub type TERMINATE_MASK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>;
63#[doc = "Field `active` reader - ??"]
64pub type ACTIVE_R = crate::BitReader<bool>;
65#[doc = "Field `lock` reader - ??"]
66pub type LOCK_R = crate::BitReader<bool>;
67#[doc = "Field `lock` writer - ??"]
68pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>;
69#[doc = "Field `halt` reader - ??"]
70pub type HALT_R = crate::BitReader<bool>;
71#[doc = "Field `halt` writer - ??"]
72pub type HALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>;
73#[doc = "Field `linked_list_counter` reader - ??"]
74pub type LINKED_LIST_COUNTER_R = crate::FieldReader<u16, u16>;
75#[doc = "Field `linked_list_counter` writer - ??"]
76pub type LINKED_LIST_COUNTER_W<'a, const O: u8> =
77 crate::FieldWriter<'a, u32, CONFIG_SPEC, u16, u16, 10, O>;
78impl R {
79 #[doc = "Bit 0 - Enable or disable DMA channel"]
80 #[inline(always)]
81 pub fn function(&self) -> FUNCTION_R {
82 FUNCTION_R::new((self.bits & 1) != 0)
83 }
84 #[doc = "Bits 1:5 - Set source peripheral for this DMA channel"]
85 #[inline(always)]
86 pub fn source_peripheral(&self) -> SOURCE_PERIPHERAL_R {
87 SOURCE_PERIPHERAL_R::new(((self.bits >> 1) & 0x1f) as u8)
88 }
89 #[doc = "Bits 6:10 - Set destination peripheral for this DMA channel"]
90 #[inline(always)]
91 pub fn destination_peripheral(&self) -> DESTINATION_PERIPHERAL_R {
92 DESTINATION_PERIPHERAL_R::new(((self.bits >> 6) & 0x1f) as u8)
93 }
94 #[doc = "Bits 11:13 - Set data direction for this channel"]
95 #[inline(always)]
96 pub fn flow_control(&self) -> FLOW_CONTROL_R {
97 FLOW_CONTROL_R::new(((self.bits >> 11) & 7) as u8)
98 }
99 #[doc = "Bit 14 - Mask error interrupt"]
100 #[inline(always)]
101 pub fn error_mask(&self) -> ERROR_MASK_R {
102 ERROR_MASK_R::new(((self.bits >> 14) & 1) != 0)
103 }
104 #[doc = "Bit 15 - Mask terminal count interrupt"]
105 #[inline(always)]
106 pub fn terminate_mask(&self) -> TERMINATE_MASK_R {
107 TERMINATE_MASK_R::new(((self.bits >> 15) & 1) != 0)
108 }
109 #[doc = "Bit 16 - ??"]
110 #[inline(always)]
111 pub fn active(&self) -> ACTIVE_R {
112 ACTIVE_R::new(((self.bits >> 16) & 1) != 0)
113 }
114 #[doc = "Bit 16 - ??"]
115 #[inline(always)]
116 pub fn lock(&self) -> LOCK_R {
117 LOCK_R::new(((self.bits >> 16) & 1) != 0)
118 }
119 #[doc = "Bit 17 - ??"]
120 #[inline(always)]
121 pub fn halt(&self) -> HALT_R {
122 HALT_R::new(((self.bits >> 17) & 1) != 0)
123 }
124 #[doc = "Bits 20:29 - ??"]
125 #[inline(always)]
126 pub fn linked_list_counter(&self) -> LINKED_LIST_COUNTER_R {
127 LINKED_LIST_COUNTER_R::new(((self.bits >> 20) & 0x03ff) as u16)
128 }
129}
130impl W {
131 #[doc = "Bit 0 - Enable or disable DMA channel"]
132 #[inline(always)]
133 #[must_use]
134 pub fn function(&mut self) -> FUNCTION_W<0> {
135 FUNCTION_W::new(self)
136 }
137 #[doc = "Bits 1:5 - Set source peripheral for this DMA channel"]
138 #[inline(always)]
139 #[must_use]
140 pub fn source_peripheral(&mut self) -> SOURCE_PERIPHERAL_W<1> {
141 SOURCE_PERIPHERAL_W::new(self)
142 }
143 #[doc = "Bits 6:10 - Set destination peripheral for this DMA channel"]
144 #[inline(always)]
145 #[must_use]
146 pub fn destination_peripheral(&mut self) -> DESTINATION_PERIPHERAL_W<6> {
147 DESTINATION_PERIPHERAL_W::new(self)
148 }
149 #[doc = "Bits 11:13 - Set data direction for this channel"]
150 #[inline(always)]
151 #[must_use]
152 pub fn flow_control(&mut self) -> FLOW_CONTROL_W<11> {
153 FLOW_CONTROL_W::new(self)
154 }
155 #[doc = "Bit 14 - Mask error interrupt"]
156 #[inline(always)]
157 #[must_use]
158 pub fn error_mask(&mut self) -> ERROR_MASK_W<14> {
159 ERROR_MASK_W::new(self)
160 }
161 #[doc = "Bit 15 - Mask terminal count interrupt"]
162 #[inline(always)]
163 #[must_use]
164 pub fn terminate_mask(&mut self) -> TERMINATE_MASK_W<15> {
165 TERMINATE_MASK_W::new(self)
166 }
167 #[doc = "Bit 16 - ??"]
168 #[inline(always)]
169 #[must_use]
170 pub fn lock(&mut self) -> LOCK_W<16> {
171 LOCK_W::new(self)
172 }
173 #[doc = "Bit 17 - ??"]
174 #[inline(always)]
175 #[must_use]
176 pub fn halt(&mut self) -> HALT_W<17> {
177 HALT_W::new(self)
178 }
179 #[doc = "Bits 20:29 - ??"]
180 #[inline(always)]
181 #[must_use]
182 pub fn linked_list_counter(&mut self) -> LINKED_LIST_COUNTER_W<20> {
183 LINKED_LIST_COUNTER_W::new(self)
184 }
185 #[doc = "Writes raw bits to the register."]
186 #[inline(always)]
187 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
188 self.0.bits(bits);
189 self
190 }
191}
192#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
193pub struct CONFIG_SPEC;
194impl crate::RegisterSpec for CONFIG_SPEC {
195 type Ux = u32;
196}
197#[doc = "`read()` method returns [config::R](R) reader structure"]
198impl crate::Readable for CONFIG_SPEC {
199 type Reader = R;
200}
201#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
202impl crate::Writable for CONFIG_SPEC {
203 type Writer = W;
204 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
205 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
206}
207#[doc = "`reset()` method sets config to value 0"]
208impl crate::Resettable for CONFIG_SPEC {
209 const RESET_VALUE: Self::Ux = 0;
210}