bl616_pac/crc/
config.rs

1#[doc = "Register `config` reader"]
2pub struct R(crate::R<CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `config` writer"]
17pub struct W(crate::W<CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Write 1 to clear internal checksum states\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq, Eq)]
39pub enum CLEAR_AW {
40    #[doc = "1: Write 1 to clear internal states"]
41    CLEAR = 1,
42}
43impl From<CLEAR_AW> for bool {
44    #[inline(always)]
45    fn from(variant: CLEAR_AW) -> Self {
46        variant as u8 != 0
47    }
48}
49#[doc = "Field `clear` writer - Write 1 to clear internal checksum states"]
50pub type CLEAR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, CLEAR_AW, O>;
51impl<'a, const O: u8> CLEAR_W<'a, O> {
52    #[doc = "Write 1 to clear internal states"]
53    #[inline(always)]
54    pub fn clear(self) -> &'a mut W {
55        self.variant(CLEAR_AW::CLEAR)
56    }
57}
58#[doc = "Field `endian` reader - Sets endian of input data"]
59pub type ENDIAN_R = crate::BitReader<ENDIAN_A>;
60#[doc = "Sets endian of input data\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum ENDIAN_A {
63    #[doc = "0: Little endian"]
64    LITTLE = 0,
65    #[doc = "1: Big endian"]
66    BIG = 1,
67}
68impl From<ENDIAN_A> for bool {
69    #[inline(always)]
70    fn from(variant: ENDIAN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl ENDIAN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub fn variant(&self) -> ENDIAN_A {
78        match self.bits {
79            false => ENDIAN_A::LITTLE,
80            true => ENDIAN_A::BIG,
81        }
82    }
83    #[doc = "Checks if the value of the field is `LITTLE`"]
84    #[inline(always)]
85    pub fn is_little(&self) -> bool {
86        *self == ENDIAN_A::LITTLE
87    }
88    #[doc = "Checks if the value of the field is `BIG`"]
89    #[inline(always)]
90    pub fn is_big(&self) -> bool {
91        *self == ENDIAN_A::BIG
92    }
93}
94#[doc = "Field `endian` writer - Sets endian of input data"]
95pub type ENDIAN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, ENDIAN_A, O>;
96impl<'a, const O: u8> ENDIAN_W<'a, O> {
97    #[doc = "Little endian"]
98    #[inline(always)]
99    pub fn little(self) -> &'a mut W {
100        self.variant(ENDIAN_A::LITTLE)
101    }
102    #[doc = "Big endian"]
103    #[inline(always)]
104    pub fn big(self) -> &'a mut W {
105        self.variant(ENDIAN_A::BIG)
106    }
107}
108impl R {
109    #[doc = "Bit 1 - Sets endian of input data"]
110    #[inline(always)]
111    pub fn endian(&self) -> ENDIAN_R {
112        ENDIAN_R::new(((self.bits >> 1) & 1) != 0)
113    }
114}
115impl W {
116    #[doc = "Bit 0 - Write 1 to clear internal checksum states"]
117    #[inline(always)]
118    #[must_use]
119    pub fn clear(&mut self) -> CLEAR_W<0> {
120        CLEAR_W::new(self)
121    }
122    #[doc = "Bit 1 - Sets endian of input data"]
123    #[inline(always)]
124    #[must_use]
125    pub fn endian(&mut self) -> ENDIAN_W<1> {
126        ENDIAN_W::new(self)
127    }
128    #[doc = "Writes raw bits to the register."]
129    #[inline(always)]
130    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
131        self.0.bits(bits);
132        self
133    }
134}
135#[doc = "Configuration register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"]
136pub struct CONFIG_SPEC;
137impl crate::RegisterSpec for CONFIG_SPEC {
138    type Ux = u32;
139}
140#[doc = "`read()` method returns [config::R](R) reader structure"]
141impl crate::Readable for CONFIG_SPEC {
142    type Reader = R;
143}
144#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"]
145impl crate::Writable for CONFIG_SPEC {
146    type Writer = W;
147    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
148    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
149}
150#[doc = "`reset()` method sets config to value 0"]
151impl crate::Resettable for CONFIG_SPEC {
152    const RESET_VALUE: Self::Ux = 0;
153}
bl616_pac/crc/config.rs

bl616_pac/crc/
config.rs
