bl616_pac/glb/
flash_config.rs

1#[doc = "Register `flash_config` reader"]
2pub struct R(crate::R<FLASH_CONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FLASH_CONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FLASH_CONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FLASH_CONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `flash_config` writer"]
17pub struct W(crate::W<FLASH_CONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FLASH_CONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FLASH_CONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FLASH_CONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `clock_divide` reader - Peripheral clock divide factor"]
38pub type CLOCK_DIVIDE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `clock_divide` writer - Peripheral clock divide factor"]
40pub type CLOCK_DIVIDE_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, FLASH_CONFIG_SPEC, u8, u8, 3, O>;
42#[doc = "Field `clock_enable` reader - Peripheral level clock gate enable"]
43pub type CLOCK_ENABLE_R = crate::BitReader<bool>;
44#[doc = "Field `clock_enable` writer - Peripheral level clock gate enable"]
45pub type CLOCK_ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, FLASH_CONFIG_SPEC, bool, O>;
46#[doc = "Field `clock_source_0` reader - Peripheral clock source register 0"]
47pub type CLOCK_SOURCE_0_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `clock_source_0` writer - Peripheral clock source register 0"]
49pub type CLOCK_SOURCE_0_W<'a, const O: u8> =
50    crate::FieldWriter<'a, u32, FLASH_CONFIG_SPEC, u8, u8, 2, O>;
51#[doc = "Field `clock_source_1` reader - Peripheral clock source register 1"]
52pub type CLOCK_SOURCE_1_R = crate::FieldReader<u8, u8>;
53#[doc = "Field `clock_source_1` writer - Peripheral clock source register 1"]
54pub type CLOCK_SOURCE_1_W<'a, const O: u8> =
55    crate::FieldWriter<'a, u32, FLASH_CONFIG_SPEC, u8, u8, 2, O>;
56impl R {
57    #[doc = "Bits 8:10 - Peripheral clock divide factor"]
58    #[inline(always)]
59    pub fn clock_divide(&self) -> CLOCK_DIVIDE_R {
60        CLOCK_DIVIDE_R::new(((self.bits >> 8) & 7) as u8)
61    }
62    #[doc = "Bit 11 - Peripheral level clock gate enable"]
63    #[inline(always)]
64    pub fn clock_enable(&self) -> CLOCK_ENABLE_R {
65        CLOCK_ENABLE_R::new(((self.bits >> 11) & 1) != 0)
66    }
67    #[doc = "Bits 12:13 - Peripheral clock source register 0"]
68    #[inline(always)]
69    pub fn clock_source_0(&self) -> CLOCK_SOURCE_0_R {
70        CLOCK_SOURCE_0_R::new(((self.bits >> 12) & 3) as u8)
71    }
72    #[doc = "Bits 14:15 - Peripheral clock source register 1"]
73    #[inline(always)]
74    pub fn clock_source_1(&self) -> CLOCK_SOURCE_1_R {
75        CLOCK_SOURCE_1_R::new(((self.bits >> 14) & 3) as u8)
76    }
77}
78impl W {
79    #[doc = "Bits 8:10 - Peripheral clock divide factor"]
80    #[inline(always)]
81    #[must_use]
82    pub fn clock_divide(&mut self) -> CLOCK_DIVIDE_W<8> {
83        CLOCK_DIVIDE_W::new(self)
84    }
85    #[doc = "Bit 11 - Peripheral level clock gate enable"]
86    #[inline(always)]
87    #[must_use]
88    pub fn clock_enable(&mut self) -> CLOCK_ENABLE_W<11> {
89        CLOCK_ENABLE_W::new(self)
90    }
91    #[doc = "Bits 12:13 - Peripheral clock source register 0"]
92    #[inline(always)]
93    #[must_use]
94    pub fn clock_source_0(&mut self) -> CLOCK_SOURCE_0_W<12> {
95        CLOCK_SOURCE_0_W::new(self)
96    }
97    #[doc = "Bits 14:15 - Peripheral clock source register 1"]
98    #[inline(always)]
99    #[must_use]
100    pub fn clock_source_1(&mut self) -> CLOCK_SOURCE_1_W<14> {
101        CLOCK_SOURCE_1_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "Serial flash configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flash_config](index.html) module"]
111pub struct FLASH_CONFIG_SPEC;
112impl crate::RegisterSpec for FLASH_CONFIG_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [flash_config::R](R) reader structure"]
116impl crate::Readable for FLASH_CONFIG_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [flash_config::W](W) writer structure"]
120impl crate::Writable for FLASH_CONFIG_SPEC {
121    type Writer = W;
122    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124}
125#[doc = "`reset()` method sets flash_config to value 0"]
126impl crate::Resettable for FLASH_CONFIG_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
bl616_pac/glb/flash_config.rs

bl616_pac/glb/
flash_config.rs
