bl616_pac/glb/
clock_config_0.rs

1#[doc = "Register `clock_config_0` reader"]
2pub struct R(crate::R<CLOCK_CONFIG_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CLOCK_CONFIG_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CLOCK_CONFIG_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CLOCK_CONFIG_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `clock_config_0` writer"]
17pub struct W(crate::W<CLOCK_CONFIG_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CLOCK_CONFIG_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CLOCK_CONFIG_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CLOCK_CONFIG_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `pll` reader - Enable or disable Phase-Locked Loop"]
38pub type PLL_R = crate::BitReader<bool>;
39#[doc = "Field `pll` writer - Enable or disable Phase-Locked Loop"]
40pub type PLL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLOCK_CONFIG_0_SPEC, bool, O>;
41#[doc = "Field `fclk` reader - Enable or disable fast clock"]
42pub type FCLK_R = crate::BitReader<bool>;
43#[doc = "Field `fclk` writer - Enable or disable fast clock"]
44pub type FCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLOCK_CONFIG_0_SPEC, bool, O>;
45#[doc = "Field `hclk` reader - Enable or disable hibernate clock"]
46pub type HCLK_R = crate::BitReader<bool>;
47#[doc = "Field `hclk` writer - Enable or disable hibernate clock"]
48pub type HCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLOCK_CONFIG_0_SPEC, bool, O>;
49#[doc = "Field `bclk` reader - Enable or disable bus clock"]
50pub type BCLK_R = crate::BitReader<bool>;
51#[doc = "Field `bclk` writer - Enable or disable bus clock"]
52pub type BCLK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CLOCK_CONFIG_0_SPEC, bool, O>;
53#[doc = "Field `root_clk_source` reader - Set source of root clock"]
54pub type ROOT_CLK_SOURCE_R = crate::FieldReader<u8, u8>;
55#[doc = "Field `root_clk_source` writer - Set source of root clock"]
56pub type ROOT_CLK_SOURCE_W<'a, const O: u8> =
57    crate::FieldWriter<'a, u32, CLOCK_CONFIG_0_SPEC, u8, u8, 2, O>;
58#[doc = "Field `hclk_divide` reader - Set divide factor of hibernate clock"]
59pub type HCLK_DIVIDE_R = crate::FieldReader<u8, u8>;
60#[doc = "Field `hclk_divide` writer - Set divide factor of hibernate clock"]
61pub type HCLK_DIVIDE_W<'a, const O: u8> =
62    crate::FieldWriter<'a, u32, CLOCK_CONFIG_0_SPEC, u8, u8, 8, O>;
63#[doc = "Field `bclk_divide` reader - Set divide factor of bus clock"]
64pub type BCLK_DIVIDE_R = crate::FieldReader<u8, u8>;
65#[doc = "Field `bclk_divide` writer - Set divide factor of bus clock"]
66pub type BCLK_DIVIDE_W<'a, const O: u8> =
67    crate::FieldWriter<'a, u32, CLOCK_CONFIG_0_SPEC, u8, u8, 8, O>;
68impl R {
69    #[doc = "Bit 0 - Enable or disable Phase-Locked Loop"]
70    #[inline(always)]
71    pub fn pll(&self) -> PLL_R {
72        PLL_R::new((self.bits & 1) != 0)
73    }
74    #[doc = "Bit 1 - Enable or disable fast clock"]
75    #[inline(always)]
76    pub fn fclk(&self) -> FCLK_R {
77        FCLK_R::new(((self.bits >> 1) & 1) != 0)
78    }
79    #[doc = "Bit 2 - Enable or disable hibernate clock"]
80    #[inline(always)]
81    pub fn hclk(&self) -> HCLK_R {
82        HCLK_R::new(((self.bits >> 2) & 1) != 0)
83    }
84    #[doc = "Bit 3 - Enable or disable bus clock"]
85    #[inline(always)]
86    pub fn bclk(&self) -> BCLK_R {
87        BCLK_R::new(((self.bits >> 3) & 1) != 0)
88    }
89    #[doc = "Bits 6:7 - Set source of root clock"]
90    #[inline(always)]
91    pub fn root_clk_source(&self) -> ROOT_CLK_SOURCE_R {
92        ROOT_CLK_SOURCE_R::new(((self.bits >> 6) & 3) as u8)
93    }
94    #[doc = "Bits 8:15 - Set divide factor of hibernate clock"]
95    #[inline(always)]
96    pub fn hclk_divide(&self) -> HCLK_DIVIDE_R {
97        HCLK_DIVIDE_R::new(((self.bits >> 8) & 0xff) as u8)
98    }
99    #[doc = "Bits 16:23 - Set divide factor of bus clock"]
100    #[inline(always)]
101    pub fn bclk_divide(&self) -> BCLK_DIVIDE_R {
102        BCLK_DIVIDE_R::new(((self.bits >> 16) & 0xff) as u8)
103    }
104}
105impl W {
106    #[doc = "Bit 0 - Enable or disable Phase-Locked Loop"]
107    #[inline(always)]
108    #[must_use]
109    pub fn pll(&mut self) -> PLL_W<0> {
110        PLL_W::new(self)
111    }
112    #[doc = "Bit 1 - Enable or disable fast clock"]
113    #[inline(always)]
114    #[must_use]
115    pub fn fclk(&mut self) -> FCLK_W<1> {
116        FCLK_W::new(self)
117    }
118    #[doc = "Bit 2 - Enable or disable hibernate clock"]
119    #[inline(always)]
120    #[must_use]
121    pub fn hclk(&mut self) -> HCLK_W<2> {
122        HCLK_W::new(self)
123    }
124    #[doc = "Bit 3 - Enable or disable bus clock"]
125    #[inline(always)]
126    #[must_use]
127    pub fn bclk(&mut self) -> BCLK_W<3> {
128        BCLK_W::new(self)
129    }
130    #[doc = "Bits 6:7 - Set source of root clock"]
131    #[inline(always)]
132    #[must_use]
133    pub fn root_clk_source(&mut self) -> ROOT_CLK_SOURCE_W<6> {
134        ROOT_CLK_SOURCE_W::new(self)
135    }
136    #[doc = "Bits 8:15 - Set divide factor of hibernate clock"]
137    #[inline(always)]
138    #[must_use]
139    pub fn hclk_divide(&mut self) -> HCLK_DIVIDE_W<8> {
140        HCLK_DIVIDE_W::new(self)
141    }
142    #[doc = "Bits 16:23 - Set divide factor of bus clock"]
143    #[inline(always)]
144    #[must_use]
145    pub fn bclk_divide(&mut self) -> BCLK_DIVIDE_W<16> {
146        BCLK_DIVIDE_W::new(self)
147    }
148    #[doc = "Writes raw bits to the register."]
149    #[inline(always)]
150    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
151        self.0.bits(bits);
152        self
153    }
154}
155#[doc = "System clock configuration register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock_config_0](index.html) module"]
156pub struct CLOCK_CONFIG_0_SPEC;
157impl crate::RegisterSpec for CLOCK_CONFIG_0_SPEC {
158    type Ux = u32;
159}
160#[doc = "`read()` method returns [clock_config_0::R](R) reader structure"]
161impl crate::Readable for CLOCK_CONFIG_0_SPEC {
162    type Reader = R;
163}
164#[doc = "`write(|w| ..)` method takes [clock_config_0::W](W) writer structure"]
165impl crate::Writable for CLOCK_CONFIG_0_SPEC {
166    type Writer = W;
167    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
168    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
169}
170#[doc = "`reset()` method sets clock_config_0 to value 0"]
171impl crate::Resettable for CLOCK_CONFIG_0_SPEC {
172    const RESET_VALUE: Self::Ux = 0;
173}
bl616_pac/glb/clock_config_0.rs

bl616_pac/glb/
clock_config_0.rs
