1use
4super::*;
5
6#[repr(C)]
7#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
8pub struct __BindgenBitfieldUnit<Storage> {
9 storage: Storage,
10}
11impl<Storage> __BindgenBitfieldUnit<Storage> {
12 #[inline]
13 pub const fn new(storage: Storage) -> Self {
14 Self { storage }
15 }
16}
17impl<Storage> __BindgenBitfieldUnit<Storage>
18where
19 Storage: AsRef<[u8]> + AsMut<[u8]>,
20{
21 #[inline]
22 pub fn get_bit(&self, index: usize) -> bool {
23 debug_assert!(index / 8 < self.storage.as_ref().len());
24 let byte_index = index / 8;
25 let byte = self.storage.as_ref()[byte_index];
26 let bit_index = if cfg!(target_endian = "big") {
27 7 - (index % 8)
28 } else {
29 index % 8
30 };
31 let mask = 1 << bit_index;
32 byte & mask == mask
33 }
34 #[inline]
35 pub fn set_bit(&mut self, index: usize, val: bool) {
36 debug_assert!(index / 8 < self.storage.as_ref().len());
37 let byte_index = index / 8;
38 let byte = &mut self.storage.as_mut()[byte_index];
39 let bit_index = if cfg!(target_endian = "big") {
40 7 - (index % 8)
41 } else {
42 index % 8
43 };
44 let mask = 1 << bit_index;
45 if val {
46 *byte |= mask;
47 } else {
48 *byte &= !mask;
49 }
50 }
51 #[inline]
52 pub fn get(&self, bit_offset: usize, bit_width: u8) -> u64 {
53 debug_assert!(bit_width <= 64);
54 debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
55 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
56 let mut val = 0;
57 for i in 0..(bit_width as usize) {
58 if self.get_bit(i + bit_offset) {
59 let index = if cfg!(target_endian = "big") {
60 bit_width as usize - 1 - i
61 } else {
62 i
63 };
64 val |= 1 << index;
65 }
66 }
67 val
68 }
69 #[inline]
70 pub fn set(&mut self, bit_offset: usize, bit_width: u8, val: u64) {
71 debug_assert!(bit_width <= 64);
72 debug_assert!(bit_offset / 8 < self.storage.as_ref().len());
73 debug_assert!((bit_offset + (bit_width as usize)) / 8 <= self.storage.as_ref().len());
74 for i in 0..(bit_width as usize) {
75 let mask = 1 << i;
76 let val_bit_is_set = val & mask == mask;
77 let index = if cfg!(target_endian = "big") {
78 bit_width as usize - 1 - i
79 } else {
80 i
81 };
82 self.set_bit(index + bit_offset, val_bit_is_set);
83 }
84 }
85}
86pub const UART_UTX_CONFIG_OFFSET: u32 = 0;
87pub const UART_CR_UTX_EN_POS: u32 = 0;
88pub const UART_CR_UTX_EN_LEN: u32 = 1;
89pub const UART_CR_UTX_EN_MSK: u32 = 1;
90pub const UART_CR_UTX_EN_UMSK: i32 = -2;
91pub const UART_CR_UTX_CTS_EN_POS: u32 = 1;
92pub const UART_CR_UTX_CTS_EN_LEN: u32 = 1;
93pub const UART_CR_UTX_CTS_EN_MSK: u32 = 2;
94pub const UART_CR_UTX_CTS_EN_UMSK: i32 = -3;
95pub const UART_CR_UTX_FRM_EN_POS: u32 = 2;
96pub const UART_CR_UTX_FRM_EN_LEN: u32 = 1;
97pub const UART_CR_UTX_FRM_EN_MSK: u32 = 4;
98pub const UART_CR_UTX_FRM_EN_UMSK: i32 = -5;
99pub const UART_CR_UTX_PRT_EN_POS: u32 = 4;
100pub const UART_CR_UTX_PRT_EN_LEN: u32 = 1;
101pub const UART_CR_UTX_PRT_EN_MSK: u32 = 16;
102pub const UART_CR_UTX_PRT_EN_UMSK: i32 = -17;
103pub const UART_CR_UTX_PRT_SEL_POS: u32 = 5;
104pub const UART_CR_UTX_PRT_SEL_LEN: u32 = 1;
105pub const UART_CR_UTX_PRT_SEL_MSK: u32 = 32;
106pub const UART_CR_UTX_PRT_SEL_UMSK: i32 = -33;
107pub const UART_CR_UTX_IR_EN_POS: u32 = 6;
108pub const UART_CR_UTX_IR_EN_LEN: u32 = 1;
109pub const UART_CR_UTX_IR_EN_MSK: u32 = 64;
110pub const UART_CR_UTX_IR_EN_UMSK: i32 = -65;
111pub const UART_CR_UTX_IR_INV_POS: u32 = 7;
112pub const UART_CR_UTX_IR_INV_LEN: u32 = 1;
113pub const UART_CR_UTX_IR_INV_MSK: u32 = 128;
114pub const UART_CR_UTX_IR_INV_UMSK: i32 = -129;
115pub const UART_CR_UTX_BIT_CNT_D_POS: u32 = 8;
116pub const UART_CR_UTX_BIT_CNT_D_LEN: u32 = 3;
117pub const UART_CR_UTX_BIT_CNT_D_MSK: u32 = 1792;
118pub const UART_CR_UTX_BIT_CNT_D_UMSK: i32 = -1793;
119pub const UART_CR_UTX_BIT_CNT_P_POS: u32 = 12;
120pub const UART_CR_UTX_BIT_CNT_P_LEN: u32 = 2;
121pub const UART_CR_UTX_BIT_CNT_P_MSK: u32 = 12288;
122pub const UART_CR_UTX_BIT_CNT_P_UMSK: i32 = -12289;
123pub const UART_CR_UTX_LEN_POS: u32 = 16;
124pub const UART_CR_UTX_LEN_LEN: u32 = 16;
125pub const UART_CR_UTX_LEN_MSK: u32 = 4294901760;
126pub const UART_CR_UTX_LEN_UMSK: i64 = -4294901761;
127pub const UART_URX_CONFIG_OFFSET: u32 = 4;
128pub const UART_CR_URX_EN_POS: u32 = 0;
129pub const UART_CR_URX_EN_LEN: u32 = 1;
130pub const UART_CR_URX_EN_MSK: u32 = 1;
131pub const UART_CR_URX_EN_UMSK: i32 = -2;
132pub const UART_CR_URX_RTS_SW_MODE_POS: u32 = 1;
133pub const UART_CR_URX_RTS_SW_MODE_LEN: u32 = 1;
134pub const UART_CR_URX_RTS_SW_MODE_MSK: u32 = 2;
135pub const UART_CR_URX_RTS_SW_MODE_UMSK: i32 = -3;
136pub const UART_CR_URX_RTS_SW_VAL_POS: u32 = 2;
137pub const UART_CR_URX_RTS_SW_VAL_LEN: u32 = 1;
138pub const UART_CR_URX_RTS_SW_VAL_MSK: u32 = 4;
139pub const UART_CR_URX_RTS_SW_VAL_UMSK: i32 = -5;
140pub const UART_CR_URX_ABR_EN_POS: u32 = 3;
141pub const UART_CR_URX_ABR_EN_LEN: u32 = 1;
142pub const UART_CR_URX_ABR_EN_MSK: u32 = 8;
143pub const UART_CR_URX_ABR_EN_UMSK: i32 = -9;
144pub const UART_CR_URX_PRT_EN_POS: u32 = 4;
145pub const UART_CR_URX_PRT_EN_LEN: u32 = 1;
146pub const UART_CR_URX_PRT_EN_MSK: u32 = 16;
147pub const UART_CR_URX_PRT_EN_UMSK: i32 = -17;
148pub const UART_CR_URX_PRT_SEL_POS: u32 = 5;
149pub const UART_CR_URX_PRT_SEL_LEN: u32 = 1;
150pub const UART_CR_URX_PRT_SEL_MSK: u32 = 32;
151pub const UART_CR_URX_PRT_SEL_UMSK: i32 = -33;
152pub const UART_CR_URX_IR_EN_POS: u32 = 6;
153pub const UART_CR_URX_IR_EN_LEN: u32 = 1;
154pub const UART_CR_URX_IR_EN_MSK: u32 = 64;
155pub const UART_CR_URX_IR_EN_UMSK: i32 = -65;
156pub const UART_CR_URX_IR_INV_POS: u32 = 7;
157pub const UART_CR_URX_IR_INV_LEN: u32 = 1;
158pub const UART_CR_URX_IR_INV_MSK: u32 = 128;
159pub const UART_CR_URX_IR_INV_UMSK: i32 = -129;
160pub const UART_CR_URX_BIT_CNT_D_POS: u32 = 8;
161pub const UART_CR_URX_BIT_CNT_D_LEN: u32 = 3;
162pub const UART_CR_URX_BIT_CNT_D_MSK: u32 = 1792;
163pub const UART_CR_URX_BIT_CNT_D_UMSK: i32 = -1793;
164pub const UART_CR_URX_DEG_EN_POS: u32 = 11;
165pub const UART_CR_URX_DEG_EN_LEN: u32 = 1;
166pub const UART_CR_URX_DEG_EN_MSK: u32 = 2048;
167pub const UART_CR_URX_DEG_EN_UMSK: i32 = -2049;
168pub const UART_CR_URX_DEG_CNT_POS: u32 = 12;
169pub const UART_CR_URX_DEG_CNT_LEN: u32 = 4;
170pub const UART_CR_URX_DEG_CNT_MSK: u32 = 61440;
171pub const UART_CR_URX_DEG_CNT_UMSK: i32 = -61441;
172pub const UART_CR_URX_LEN_POS: u32 = 16;
173pub const UART_CR_URX_LEN_LEN: u32 = 16;
174pub const UART_CR_URX_LEN_MSK: u32 = 4294901760;
175pub const UART_CR_URX_LEN_UMSK: i64 = -4294901761;
176pub const UART_BIT_PRD_OFFSET: u32 = 8;
177pub const UART_CR_UTX_BIT_PRD_POS: u32 = 0;
178pub const UART_CR_UTX_BIT_PRD_LEN: u32 = 16;
179pub const UART_CR_UTX_BIT_PRD_MSK: u32 = 65535;
180pub const UART_CR_UTX_BIT_PRD_UMSK: i32 = -65536;
181pub const UART_CR_URX_BIT_PRD_POS: u32 = 16;
182pub const UART_CR_URX_BIT_PRD_LEN: u32 = 16;
183pub const UART_CR_URX_BIT_PRD_MSK: u32 = 4294901760;
184pub const UART_CR_URX_BIT_PRD_UMSK: i64 = -4294901761;
185pub const UART_DATA_CONFIG_OFFSET: u32 = 12;
186pub const UART_CR_UART_BIT_INV_POS: u32 = 0;
187pub const UART_CR_UART_BIT_INV_LEN: u32 = 1;
188pub const UART_CR_UART_BIT_INV_MSK: u32 = 1;
189pub const UART_CR_UART_BIT_INV_UMSK: i32 = -2;
190pub const UART_UTX_IR_POSITION_OFFSET: u32 = 16;
191pub const UART_CR_UTX_IR_POS_S_POS: u32 = 0;
192pub const UART_CR_UTX_IR_POS_S_LEN: u32 = 16;
193pub const UART_CR_UTX_IR_POS_S_MSK: u32 = 65535;
194pub const UART_CR_UTX_IR_POS_S_UMSK: i32 = -65536;
195pub const UART_CR_UTX_IR_POS_P_POS: u32 = 16;
196pub const UART_CR_UTX_IR_POS_P_LEN: u32 = 16;
197pub const UART_CR_UTX_IR_POS_P_MSK: u32 = 4294901760;
198pub const UART_CR_UTX_IR_POS_P_UMSK: i64 = -4294901761;
199pub const UART_URX_IR_POSITION_OFFSET: u32 = 20;
200pub const UART_CR_URX_IR_POS_S_POS: u32 = 0;
201pub const UART_CR_URX_IR_POS_S_LEN: u32 = 16;
202pub const UART_CR_URX_IR_POS_S_MSK: u32 = 65535;
203pub const UART_CR_URX_IR_POS_S_UMSK: i32 = -65536;
204pub const UART_URX_RTO_TIMER_OFFSET: u32 = 24;
205pub const UART_CR_URX_RTO_VALUE_POS: u32 = 0;
206pub const UART_CR_URX_RTO_VALUE_LEN: u32 = 8;
207pub const UART_CR_URX_RTO_VALUE_MSK: u32 = 255;
208pub const UART_CR_URX_RTO_VALUE_UMSK: i32 = -256;
209pub const UART_INT_STS_OFFSET: u32 = 32;
210pub const UART_UTX_END_INT_POS: u32 = 0;
211pub const UART_UTX_END_INT_LEN: u32 = 1;
212pub const UART_UTX_END_INT_MSK: u32 = 1;
213pub const UART_UTX_END_INT_UMSK: i32 = -2;
214pub const UART_URX_END_INT_POS: u32 = 1;
215pub const UART_URX_END_INT_LEN: u32 = 1;
216pub const UART_URX_END_INT_MSK: u32 = 2;
217pub const UART_URX_END_INT_UMSK: i32 = -3;
218pub const UART_UTX_FIFO_INT_POS: u32 = 2;
219pub const UART_UTX_FIFO_INT_LEN: u32 = 1;
220pub const UART_UTX_FIFO_INT_MSK: u32 = 4;
221pub const UART_UTX_FIFO_INT_UMSK: i32 = -5;
222pub const UART_URX_FIFO_INT_POS: u32 = 3;
223pub const UART_URX_FIFO_INT_LEN: u32 = 1;
224pub const UART_URX_FIFO_INT_MSK: u32 = 8;
225pub const UART_URX_FIFO_INT_UMSK: i32 = -9;
226pub const UART_URX_RTO_INT_POS: u32 = 4;
227pub const UART_URX_RTO_INT_LEN: u32 = 1;
228pub const UART_URX_RTO_INT_MSK: u32 = 16;
229pub const UART_URX_RTO_INT_UMSK: i32 = -17;
230pub const UART_URX_PCE_INT_POS: u32 = 5;
231pub const UART_URX_PCE_INT_LEN: u32 = 1;
232pub const UART_URX_PCE_INT_MSK: u32 = 32;
233pub const UART_URX_PCE_INT_UMSK: i32 = -33;
234pub const UART_UTX_FER_INT_POS: u32 = 6;
235pub const UART_UTX_FER_INT_LEN: u32 = 1;
236pub const UART_UTX_FER_INT_MSK: u32 = 64;
237pub const UART_UTX_FER_INT_UMSK: i32 = -65;
238pub const UART_URX_FER_INT_POS: u32 = 7;
239pub const UART_URX_FER_INT_LEN: u32 = 1;
240pub const UART_URX_FER_INT_MSK: u32 = 128;
241pub const UART_URX_FER_INT_UMSK: i32 = -129;
242pub const UART_INT_MASK_OFFSET: u32 = 36;
243pub const UART_CR_UTX_END_MASK_POS: u32 = 0;
244pub const UART_CR_UTX_END_MASK_LEN: u32 = 1;
245pub const UART_CR_UTX_END_MASK_MSK: u32 = 1;
246pub const UART_CR_UTX_END_MASK_UMSK: i32 = -2;
247pub const UART_CR_URX_END_MASK_POS: u32 = 1;
248pub const UART_CR_URX_END_MASK_LEN: u32 = 1;
249pub const UART_CR_URX_END_MASK_MSK: u32 = 2;
250pub const UART_CR_URX_END_MASK_UMSK: i32 = -3;
251pub const UART_CR_UTX_FIFO_MASK_POS: u32 = 2;
252pub const UART_CR_UTX_FIFO_MASK_LEN: u32 = 1;
253pub const UART_CR_UTX_FIFO_MASK_MSK: u32 = 4;
254pub const UART_CR_UTX_FIFO_MASK_UMSK: i32 = -5;
255pub const UART_CR_URX_FIFO_MASK_POS: u32 = 3;
256pub const UART_CR_URX_FIFO_MASK_LEN: u32 = 1;
257pub const UART_CR_URX_FIFO_MASK_MSK: u32 = 8;
258pub const UART_CR_URX_FIFO_MASK_UMSK: i32 = -9;
259pub const UART_CR_URX_RTO_MASK_POS: u32 = 4;
260pub const UART_CR_URX_RTO_MASK_LEN: u32 = 1;
261pub const UART_CR_URX_RTO_MASK_MSK: u32 = 16;
262pub const UART_CR_URX_RTO_MASK_UMSK: i32 = -17;
263pub const UART_CR_URX_PCE_MASK_POS: u32 = 5;
264pub const UART_CR_URX_PCE_MASK_LEN: u32 = 1;
265pub const UART_CR_URX_PCE_MASK_MSK: u32 = 32;
266pub const UART_CR_URX_PCE_MASK_UMSK: i32 = -33;
267pub const UART_CR_UTX_FER_MASK_POS: u32 = 6;
268pub const UART_CR_UTX_FER_MASK_LEN: u32 = 1;
269pub const UART_CR_UTX_FER_MASK_MSK: u32 = 64;
270pub const UART_CR_UTX_FER_MASK_UMSK: i32 = -65;
271pub const UART_CR_URX_FER_MASK_POS: u32 = 7;
272pub const UART_CR_URX_FER_MASK_LEN: u32 = 1;
273pub const UART_CR_URX_FER_MASK_MSK: u32 = 128;
274pub const UART_CR_URX_FER_MASK_UMSK: i32 = -129;
275pub const UART_INT_CLEAR_OFFSET: u32 = 40;
276pub const UART_CR_UTX_END_CLR_POS: u32 = 0;
277pub const UART_CR_UTX_END_CLR_LEN: u32 = 1;
278pub const UART_CR_UTX_END_CLR_MSK: u32 = 1;
279pub const UART_CR_UTX_END_CLR_UMSK: i32 = -2;
280pub const UART_CR_URX_END_CLR_POS: u32 = 1;
281pub const UART_CR_URX_END_CLR_LEN: u32 = 1;
282pub const UART_CR_URX_END_CLR_MSK: u32 = 2;
283pub const UART_CR_URX_END_CLR_UMSK: i32 = -3;
284pub const UART_CR_URX_RTO_CLR_POS: u32 = 4;
285pub const UART_CR_URX_RTO_CLR_LEN: u32 = 1;
286pub const UART_CR_URX_RTO_CLR_MSK: u32 = 16;
287pub const UART_CR_URX_RTO_CLR_UMSK: i32 = -17;
288pub const UART_CR_URX_PCE_CLR_POS: u32 = 5;
289pub const UART_CR_URX_PCE_CLR_LEN: u32 = 1;
290pub const UART_CR_URX_PCE_CLR_MSK: u32 = 32;
291pub const UART_CR_URX_PCE_CLR_UMSK: i32 = -33;
292pub const UART_INT_EN_OFFSET: u32 = 44;
293pub const UART_CR_UTX_END_EN_POS: u32 = 0;
294pub const UART_CR_UTX_END_EN_LEN: u32 = 1;
295pub const UART_CR_UTX_END_EN_MSK: u32 = 1;
296pub const UART_CR_UTX_END_EN_UMSK: i32 = -2;
297pub const UART_CR_URX_END_EN_POS: u32 = 1;
298pub const UART_CR_URX_END_EN_LEN: u32 = 1;
299pub const UART_CR_URX_END_EN_MSK: u32 = 2;
300pub const UART_CR_URX_END_EN_UMSK: i32 = -3;
301pub const UART_CR_UTX_FIFO_EN_POS: u32 = 2;
302pub const UART_CR_UTX_FIFO_EN_LEN: u32 = 1;
303pub const UART_CR_UTX_FIFO_EN_MSK: u32 = 4;
304pub const UART_CR_UTX_FIFO_EN_UMSK: i32 = -5;
305pub const UART_CR_URX_FIFO_EN_POS: u32 = 3;
306pub const UART_CR_URX_FIFO_EN_LEN: u32 = 1;
307pub const UART_CR_URX_FIFO_EN_MSK: u32 = 8;
308pub const UART_CR_URX_FIFO_EN_UMSK: i32 = -9;
309pub const UART_CR_URX_RTO_EN_POS: u32 = 4;
310pub const UART_CR_URX_RTO_EN_LEN: u32 = 1;
311pub const UART_CR_URX_RTO_EN_MSK: u32 = 16;
312pub const UART_CR_URX_RTO_EN_UMSK: i32 = -17;
313pub const UART_CR_URX_PCE_EN_POS: u32 = 5;
314pub const UART_CR_URX_PCE_EN_LEN: u32 = 1;
315pub const UART_CR_URX_PCE_EN_MSK: u32 = 32;
316pub const UART_CR_URX_PCE_EN_UMSK: i32 = -33;
317pub const UART_CR_UTX_FER_EN_POS: u32 = 6;
318pub const UART_CR_UTX_FER_EN_LEN: u32 = 1;
319pub const UART_CR_UTX_FER_EN_MSK: u32 = 64;
320pub const UART_CR_UTX_FER_EN_UMSK: i32 = -65;
321pub const UART_CR_URX_FER_EN_POS: u32 = 7;
322pub const UART_CR_URX_FER_EN_LEN: u32 = 1;
323pub const UART_CR_URX_FER_EN_MSK: u32 = 128;
324pub const UART_CR_URX_FER_EN_UMSK: i32 = -129;
325pub const UART_STATUS_OFFSET: u32 = 48;
326pub const UART_STS_UTX_BUS_BUSY_POS: u32 = 0;
327pub const UART_STS_UTX_BUS_BUSY_LEN: u32 = 1;
328pub const UART_STS_UTX_BUS_BUSY_MSK: u32 = 1;
329pub const UART_STS_UTX_BUS_BUSY_UMSK: i32 = -2;
330pub const UART_STS_URX_BUS_BUSY_POS: u32 = 1;
331pub const UART_STS_URX_BUS_BUSY_LEN: u32 = 1;
332pub const UART_STS_URX_BUS_BUSY_MSK: u32 = 2;
333pub const UART_STS_URX_BUS_BUSY_UMSK: i32 = -3;
334pub const UART_STS_URX_ABR_PRD_OFFSET: u32 = 52;
335pub const UART_STS_URX_ABR_PRD_START_POS: u32 = 0;
336pub const UART_STS_URX_ABR_PRD_START_LEN: u32 = 16;
337pub const UART_STS_URX_ABR_PRD_START_MSK: u32 = 65535;
338pub const UART_STS_URX_ABR_PRD_START_UMSK: i32 = -65536;
339pub const UART_STS_URX_ABR_PRD_0X55_POS: u32 = 16;
340pub const UART_STS_URX_ABR_PRD_0X55_LEN: u32 = 16;
341pub const UART_STS_URX_ABR_PRD_0X55_MSK: u32 = 4294901760;
342pub const UART_STS_URX_ABR_PRD_0X55_UMSK: i64 = -4294901761;
343pub const UART_FIFO_CONFIG_0_OFFSET: u32 = 128;
344pub const UART_DMA_TX_EN_POS: u32 = 0;
345pub const UART_DMA_TX_EN_LEN: u32 = 1;
346pub const UART_DMA_TX_EN_MSK: u32 = 1;
347pub const UART_DMA_TX_EN_UMSK: i32 = -2;
348pub const UART_DMA_RX_EN_POS: u32 = 1;
349pub const UART_DMA_RX_EN_LEN: u32 = 1;
350pub const UART_DMA_RX_EN_MSK: u32 = 2;
351pub const UART_DMA_RX_EN_UMSK: i32 = -3;
352pub const UART_TX_FIFO_CLR_POS: u32 = 2;
353pub const UART_TX_FIFO_CLR_LEN: u32 = 1;
354pub const UART_TX_FIFO_CLR_MSK: u32 = 4;
355pub const UART_TX_FIFO_CLR_UMSK: i32 = -5;
356pub const UART_RX_FIFO_CLR_POS: u32 = 3;
357pub const UART_RX_FIFO_CLR_LEN: u32 = 1;
358pub const UART_RX_FIFO_CLR_MSK: u32 = 8;
359pub const UART_RX_FIFO_CLR_UMSK: i32 = -9;
360pub const UART_TX_FIFO_OVERFLOW_POS: u32 = 4;
361pub const UART_TX_FIFO_OVERFLOW_LEN: u32 = 1;
362pub const UART_TX_FIFO_OVERFLOW_MSK: u32 = 16;
363pub const UART_TX_FIFO_OVERFLOW_UMSK: i32 = -17;
364pub const UART_TX_FIFO_UNDERFLOW_POS: u32 = 5;
365pub const UART_TX_FIFO_UNDERFLOW_LEN: u32 = 1;
366pub const UART_TX_FIFO_UNDERFLOW_MSK: u32 = 32;
367pub const UART_TX_FIFO_UNDERFLOW_UMSK: i32 = -33;
368pub const UART_RX_FIFO_OVERFLOW_POS: u32 = 6;
369pub const UART_RX_FIFO_OVERFLOW_LEN: u32 = 1;
370pub const UART_RX_FIFO_OVERFLOW_MSK: u32 = 64;
371pub const UART_RX_FIFO_OVERFLOW_UMSK: i32 = -65;
372pub const UART_RX_FIFO_UNDERFLOW_POS: u32 = 7;
373pub const UART_RX_FIFO_UNDERFLOW_LEN: u32 = 1;
374pub const UART_RX_FIFO_UNDERFLOW_MSK: u32 = 128;
375pub const UART_RX_FIFO_UNDERFLOW_UMSK: i32 = -129;
376pub const UART_FIFO_CONFIG_1_OFFSET: u32 = 132;
377pub const UART_TX_FIFO_CNT_POS: u32 = 0;
378pub const UART_TX_FIFO_CNT_LEN: u32 = 6;
379pub const UART_TX_FIFO_CNT_MSK: u32 = 63;
380pub const UART_TX_FIFO_CNT_UMSK: i32 = -64;
381pub const UART_RX_FIFO_CNT_POS: u32 = 8;
382pub const UART_RX_FIFO_CNT_LEN: u32 = 6;
383pub const UART_RX_FIFO_CNT_MSK: u32 = 16128;
384pub const UART_RX_FIFO_CNT_UMSK: i32 = -16129;
385pub const UART_TX_FIFO_TH_POS: u32 = 16;
386pub const UART_TX_FIFO_TH_LEN: u32 = 5;
387pub const UART_TX_FIFO_TH_MSK: u32 = 2031616;
388pub const UART_TX_FIFO_TH_UMSK: i32 = -2031617;
389pub const UART_RX_FIFO_TH_POS: u32 = 24;
390pub const UART_RX_FIFO_TH_LEN: u32 = 5;
391pub const UART_RX_FIFO_TH_MSK: u32 = 520093696;
392pub const UART_RX_FIFO_TH_UMSK: i32 = -520093697;
393pub const UART_FIFO_WDATA_OFFSET: u32 = 136;
394pub const UART_FIFO_WDATA_POS: u32 = 0;
395pub const UART_FIFO_WDATA_LEN: u32 = 8;
396pub const UART_FIFO_WDATA_MSK: u32 = 255;
397pub const UART_FIFO_WDATA_UMSK: i32 = -256;
398pub const UART_FIFO_RDATA_OFFSET: u32 = 140;
399pub const UART_FIFO_RDATA_POS: u32 = 0;
400pub const UART_FIFO_RDATA_LEN: u32 = 8;
401pub const UART_FIFO_RDATA_MSK: u32 = 255;
402pub const UART_FIFO_RDATA_UMSK: i32 = -256;
403pub const UART_RX_FIFO_SIZE: u32 = 32;
404pub const UART_TX_FIFO_SIZE: u32 = 32;
405pub const UART_DEFAULT_RECV_TIMEOUT: u32 = 80;
406pub const BL_UART_BUFFER_SIZE_MIN: u32 = 128;
407pub const BL_UART_BUFFER_SIZE_MASK: u32 = 127;
408pub type __uint8_t = ::cty::c_uchar;
409pub type __uint16_t = ::cty::c_ushort;
410pub type __uint32_t = ::cty::c_uint;
411#[repr(C)]
412#[derive(Copy, Clone)]
413pub struct uart_reg {
414 pub utx_config: uart_reg__bindgen_ty_1,
415 pub urx_config: uart_reg__bindgen_ty_2,
416 pub uart_bit_prd: uart_reg__bindgen_ty_3,
417 pub data_config: uart_reg__bindgen_ty_4,
418 pub utx_ir_position: uart_reg__bindgen_ty_5,
419 pub urx_ir_position: uart_reg__bindgen_ty_6,
420 pub urx_rto_timer: uart_reg__bindgen_ty_7,
421 pub RESERVED0x1c: [u8; 4usize],
422 pub uart_int_sts: uart_reg__bindgen_ty_8,
423 pub uart_int_mask: uart_reg__bindgen_ty_9,
424 pub uart_int_clear: uart_reg__bindgen_ty_10,
425 pub uart_int_en: uart_reg__bindgen_ty_11,
426 pub uart_status: uart_reg__bindgen_ty_12,
427 pub sts_urx_abr_prd: uart_reg__bindgen_ty_13,
428 pub RESERVED0x38: [u8; 72usize],
429 pub uart_fifo_config_0: uart_reg__bindgen_ty_14,
430 pub uart_fifo_config_1: uart_reg__bindgen_ty_15,
431 pub uart_fifo_wdata: uart_reg__bindgen_ty_16,
432 pub uart_fifo_rdata: uart_reg__bindgen_ty_17,
433}
434#[repr(C)]
435#[derive(Copy, Clone)]
436pub union uart_reg__bindgen_ty_1 {
437 pub BF: uart_reg__bindgen_ty_1__bindgen_ty_1,
438 pub WORD: u32,
439}
440#[repr(C)]
441#[repr(align(4))]
442#[derive(Default, Copy, Clone)]
443pub struct uart_reg__bindgen_ty_1__bindgen_ty_1 {
444 pub _bitfield_align_1: [u16; 0],
445 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
446}
447impl uart_reg__bindgen_ty_1__bindgen_ty_1 {
448 #[inline]
449 pub fn cr_utx_en(&self) -> u32 {
450 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
451 }
452 #[inline]
453 pub fn set_cr_utx_en(&mut self, val: u32) {
454 unsafe {
455 let val: u32 = ::core::mem::transmute(val);
456 self._bitfield_1.set(0usize, 1u8, val as u64)
457 }
458 }
459 #[inline]
460 pub fn cr_utx_cts_en(&self) -> u32 {
461 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
462 }
463 #[inline]
464 pub fn set_cr_utx_cts_en(&mut self, val: u32) {
465 unsafe {
466 let val: u32 = ::core::mem::transmute(val);
467 self._bitfield_1.set(1usize, 1u8, val as u64)
468 }
469 }
470 #[inline]
471 pub fn cr_utx_frm_en(&self) -> u32 {
472 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
473 }
474 #[inline]
475 pub fn set_cr_utx_frm_en(&mut self, val: u32) {
476 unsafe {
477 let val: u32 = ::core::mem::transmute(val);
478 self._bitfield_1.set(2usize, 1u8, val as u64)
479 }
480 }
481 #[inline]
482 pub fn reserved_3(&self) -> u32 {
483 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
484 }
485 #[inline]
486 pub fn set_reserved_3(&mut self, val: u32) {
487 unsafe {
488 let val: u32 = ::core::mem::transmute(val);
489 self._bitfield_1.set(3usize, 1u8, val as u64)
490 }
491 }
492 #[inline]
493 pub fn cr_utx_prt_en(&self) -> u32 {
494 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
495 }
496 #[inline]
497 pub fn set_cr_utx_prt_en(&mut self, val: u32) {
498 unsafe {
499 let val: u32 = ::core::mem::transmute(val);
500 self._bitfield_1.set(4usize, 1u8, val as u64)
501 }
502 }
503 #[inline]
504 pub fn cr_utx_prt_sel(&self) -> u32 {
505 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
506 }
507 #[inline]
508 pub fn set_cr_utx_prt_sel(&mut self, val: u32) {
509 unsafe {
510 let val: u32 = ::core::mem::transmute(val);
511 self._bitfield_1.set(5usize, 1u8, val as u64)
512 }
513 }
514 #[inline]
515 pub fn cr_utx_ir_en(&self) -> u32 {
516 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
517 }
518 #[inline]
519 pub fn set_cr_utx_ir_en(&mut self, val: u32) {
520 unsafe {
521 let val: u32 = ::core::mem::transmute(val);
522 self._bitfield_1.set(6usize, 1u8, val as u64)
523 }
524 }
525 #[inline]
526 pub fn cr_utx_ir_inv(&self) -> u32 {
527 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
528 }
529 #[inline]
530 pub fn set_cr_utx_ir_inv(&mut self, val: u32) {
531 unsafe {
532 let val: u32 = ::core::mem::transmute(val);
533 self._bitfield_1.set(7usize, 1u8, val as u64)
534 }
535 }
536 #[inline]
537 pub fn cr_utx_bit_cnt_d(&self) -> u32 {
538 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 3u8) as u32) }
539 }
540 #[inline]
541 pub fn set_cr_utx_bit_cnt_d(&mut self, val: u32) {
542 unsafe {
543 let val: u32 = ::core::mem::transmute(val);
544 self._bitfield_1.set(8usize, 3u8, val as u64)
545 }
546 }
547 #[inline]
548 pub fn reserved_11(&self) -> u32 {
549 unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
550 }
551 #[inline]
552 pub fn set_reserved_11(&mut self, val: u32) {
553 unsafe {
554 let val: u32 = ::core::mem::transmute(val);
555 self._bitfield_1.set(11usize, 1u8, val as u64)
556 }
557 }
558 #[inline]
559 pub fn cr_utx_bit_cnt_p(&self) -> u32 {
560 unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 2u8) as u32) }
561 }
562 #[inline]
563 pub fn set_cr_utx_bit_cnt_p(&mut self, val: u32) {
564 unsafe {
565 let val: u32 = ::core::mem::transmute(val);
566 self._bitfield_1.set(12usize, 2u8, val as u64)
567 }
568 }
569 #[inline]
570 pub fn reserved_14_15(&self) -> u32 {
571 unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 2u8) as u32) }
572 }
573 #[inline]
574 pub fn set_reserved_14_15(&mut self, val: u32) {
575 unsafe {
576 let val: u32 = ::core::mem::transmute(val);
577 self._bitfield_1.set(14usize, 2u8, val as u64)
578 }
579 }
580 #[inline]
581 pub fn cr_utx_len(&self) -> u32 {
582 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
583 }
584 #[inline]
585 pub fn set_cr_utx_len(&mut self, val: u32) {
586 unsafe {
587 let val: u32 = ::core::mem::transmute(val);
588 self._bitfield_1.set(16usize, 16u8, val as u64)
589 }
590 }
591 #[inline]
592 pub fn new_bitfield_1(
593 cr_utx_en: u32,
594 cr_utx_cts_en: u32,
595 cr_utx_frm_en: u32,
596 reserved_3: u32,
597 cr_utx_prt_en: u32,
598 cr_utx_prt_sel: u32,
599 cr_utx_ir_en: u32,
600 cr_utx_ir_inv: u32,
601 cr_utx_bit_cnt_d: u32,
602 reserved_11: u32,
603 cr_utx_bit_cnt_p: u32,
604 reserved_14_15: u32,
605 cr_utx_len: u32,
606 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
607 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
608 __bindgen_bitfield_unit.set(0usize, 1u8, {
609 let cr_utx_en: u32 = unsafe { ::core::mem::transmute(cr_utx_en) };
610 cr_utx_en as u64
611 });
612 __bindgen_bitfield_unit.set(1usize, 1u8, {
613 let cr_utx_cts_en: u32 = unsafe { ::core::mem::transmute(cr_utx_cts_en) };
614 cr_utx_cts_en as u64
615 });
616 __bindgen_bitfield_unit.set(2usize, 1u8, {
617 let cr_utx_frm_en: u32 = unsafe { ::core::mem::transmute(cr_utx_frm_en) };
618 cr_utx_frm_en as u64
619 });
620 __bindgen_bitfield_unit.set(3usize, 1u8, {
621 let reserved_3: u32 = unsafe { ::core::mem::transmute(reserved_3) };
622 reserved_3 as u64
623 });
624 __bindgen_bitfield_unit.set(4usize, 1u8, {
625 let cr_utx_prt_en: u32 = unsafe { ::core::mem::transmute(cr_utx_prt_en) };
626 cr_utx_prt_en as u64
627 });
628 __bindgen_bitfield_unit.set(5usize, 1u8, {
629 let cr_utx_prt_sel: u32 = unsafe { ::core::mem::transmute(cr_utx_prt_sel) };
630 cr_utx_prt_sel as u64
631 });
632 __bindgen_bitfield_unit.set(6usize, 1u8, {
633 let cr_utx_ir_en: u32 = unsafe { ::core::mem::transmute(cr_utx_ir_en) };
634 cr_utx_ir_en as u64
635 });
636 __bindgen_bitfield_unit.set(7usize, 1u8, {
637 let cr_utx_ir_inv: u32 = unsafe { ::core::mem::transmute(cr_utx_ir_inv) };
638 cr_utx_ir_inv as u64
639 });
640 __bindgen_bitfield_unit.set(8usize, 3u8, {
641 let cr_utx_bit_cnt_d: u32 = unsafe { ::core::mem::transmute(cr_utx_bit_cnt_d) };
642 cr_utx_bit_cnt_d as u64
643 });
644 __bindgen_bitfield_unit.set(11usize, 1u8, {
645 let reserved_11: u32 = unsafe { ::core::mem::transmute(reserved_11) };
646 reserved_11 as u64
647 });
648 __bindgen_bitfield_unit.set(12usize, 2u8, {
649 let cr_utx_bit_cnt_p: u32 = unsafe { ::core::mem::transmute(cr_utx_bit_cnt_p) };
650 cr_utx_bit_cnt_p as u64
651 });
652 __bindgen_bitfield_unit.set(14usize, 2u8, {
653 let reserved_14_15: u32 = unsafe { ::core::mem::transmute(reserved_14_15) };
654 reserved_14_15 as u64
655 });
656 __bindgen_bitfield_unit.set(16usize, 16u8, {
657 let cr_utx_len: u32 = unsafe { ::core::mem::transmute(cr_utx_len) };
658 cr_utx_len as u64
659 });
660 __bindgen_bitfield_unit
661 }
662}
663impl Default for uart_reg__bindgen_ty_1 {
664 fn default() -> Self {
665 unsafe { ::core::mem::zeroed() }
666 }
667}
668#[repr(C)]
669#[derive(Copy, Clone)]
670pub union uart_reg__bindgen_ty_2 {
671 pub BF: uart_reg__bindgen_ty_2__bindgen_ty_1,
672 pub WORD: u32,
673}
674#[repr(C)]
675#[repr(align(4))]
676#[derive(Default, Copy, Clone)]
677pub struct uart_reg__bindgen_ty_2__bindgen_ty_1 {
678 pub _bitfield_align_1: [u16; 0],
679 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
680}
681impl uart_reg__bindgen_ty_2__bindgen_ty_1 {
682 #[inline]
683 pub fn cr_urx_en(&self) -> u32 {
684 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
685 }
686 #[inline]
687 pub fn set_cr_urx_en(&mut self, val: u32) {
688 unsafe {
689 let val: u32 = ::core::mem::transmute(val);
690 self._bitfield_1.set(0usize, 1u8, val as u64)
691 }
692 }
693 #[inline]
694 pub fn cr_urx_rts_sw_mode(&self) -> u32 {
695 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
696 }
697 #[inline]
698 pub fn set_cr_urx_rts_sw_mode(&mut self, val: u32) {
699 unsafe {
700 let val: u32 = ::core::mem::transmute(val);
701 self._bitfield_1.set(1usize, 1u8, val as u64)
702 }
703 }
704 #[inline]
705 pub fn cr_urx_rts_sw_val(&self) -> u32 {
706 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
707 }
708 #[inline]
709 pub fn set_cr_urx_rts_sw_val(&mut self, val: u32) {
710 unsafe {
711 let val: u32 = ::core::mem::transmute(val);
712 self._bitfield_1.set(2usize, 1u8, val as u64)
713 }
714 }
715 #[inline]
716 pub fn cr_urx_abr_en(&self) -> u32 {
717 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
718 }
719 #[inline]
720 pub fn set_cr_urx_abr_en(&mut self, val: u32) {
721 unsafe {
722 let val: u32 = ::core::mem::transmute(val);
723 self._bitfield_1.set(3usize, 1u8, val as u64)
724 }
725 }
726 #[inline]
727 pub fn cr_urx_prt_en(&self) -> u32 {
728 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
729 }
730 #[inline]
731 pub fn set_cr_urx_prt_en(&mut self, val: u32) {
732 unsafe {
733 let val: u32 = ::core::mem::transmute(val);
734 self._bitfield_1.set(4usize, 1u8, val as u64)
735 }
736 }
737 #[inline]
738 pub fn cr_urx_prt_sel(&self) -> u32 {
739 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
740 }
741 #[inline]
742 pub fn set_cr_urx_prt_sel(&mut self, val: u32) {
743 unsafe {
744 let val: u32 = ::core::mem::transmute(val);
745 self._bitfield_1.set(5usize, 1u8, val as u64)
746 }
747 }
748 #[inline]
749 pub fn cr_urx_ir_en(&self) -> u32 {
750 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
751 }
752 #[inline]
753 pub fn set_cr_urx_ir_en(&mut self, val: u32) {
754 unsafe {
755 let val: u32 = ::core::mem::transmute(val);
756 self._bitfield_1.set(6usize, 1u8, val as u64)
757 }
758 }
759 #[inline]
760 pub fn cr_urx_ir_inv(&self) -> u32 {
761 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
762 }
763 #[inline]
764 pub fn set_cr_urx_ir_inv(&mut self, val: u32) {
765 unsafe {
766 let val: u32 = ::core::mem::transmute(val);
767 self._bitfield_1.set(7usize, 1u8, val as u64)
768 }
769 }
770 #[inline]
771 pub fn cr_urx_bit_cnt_d(&self) -> u32 {
772 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 3u8) as u32) }
773 }
774 #[inline]
775 pub fn set_cr_urx_bit_cnt_d(&mut self, val: u32) {
776 unsafe {
777 let val: u32 = ::core::mem::transmute(val);
778 self._bitfield_1.set(8usize, 3u8, val as u64)
779 }
780 }
781 #[inline]
782 pub fn cr_urx_deg_en(&self) -> u32 {
783 unsafe { ::core::mem::transmute(self._bitfield_1.get(11usize, 1u8) as u32) }
784 }
785 #[inline]
786 pub fn set_cr_urx_deg_en(&mut self, val: u32) {
787 unsafe {
788 let val: u32 = ::core::mem::transmute(val);
789 self._bitfield_1.set(11usize, 1u8, val as u64)
790 }
791 }
792 #[inline]
793 pub fn cr_urx_deg_cnt(&self) -> u32 {
794 unsafe { ::core::mem::transmute(self._bitfield_1.get(12usize, 4u8) as u32) }
795 }
796 #[inline]
797 pub fn set_cr_urx_deg_cnt(&mut self, val: u32) {
798 unsafe {
799 let val: u32 = ::core::mem::transmute(val);
800 self._bitfield_1.set(12usize, 4u8, val as u64)
801 }
802 }
803 #[inline]
804 pub fn cr_urx_len(&self) -> u32 {
805 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
806 }
807 #[inline]
808 pub fn set_cr_urx_len(&mut self, val: u32) {
809 unsafe {
810 let val: u32 = ::core::mem::transmute(val);
811 self._bitfield_1.set(16usize, 16u8, val as u64)
812 }
813 }
814 #[inline]
815 pub fn new_bitfield_1(
816 cr_urx_en: u32,
817 cr_urx_rts_sw_mode: u32,
818 cr_urx_rts_sw_val: u32,
819 cr_urx_abr_en: u32,
820 cr_urx_prt_en: u32,
821 cr_urx_prt_sel: u32,
822 cr_urx_ir_en: u32,
823 cr_urx_ir_inv: u32,
824 cr_urx_bit_cnt_d: u32,
825 cr_urx_deg_en: u32,
826 cr_urx_deg_cnt: u32,
827 cr_urx_len: u32,
828 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
829 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
830 __bindgen_bitfield_unit.set(0usize, 1u8, {
831 let cr_urx_en: u32 = unsafe { ::core::mem::transmute(cr_urx_en) };
832 cr_urx_en as u64
833 });
834 __bindgen_bitfield_unit.set(1usize, 1u8, {
835 let cr_urx_rts_sw_mode: u32 = unsafe { ::core::mem::transmute(cr_urx_rts_sw_mode) };
836 cr_urx_rts_sw_mode as u64
837 });
838 __bindgen_bitfield_unit.set(2usize, 1u8, {
839 let cr_urx_rts_sw_val: u32 = unsafe { ::core::mem::transmute(cr_urx_rts_sw_val) };
840 cr_urx_rts_sw_val as u64
841 });
842 __bindgen_bitfield_unit.set(3usize, 1u8, {
843 let cr_urx_abr_en: u32 = unsafe { ::core::mem::transmute(cr_urx_abr_en) };
844 cr_urx_abr_en as u64
845 });
846 __bindgen_bitfield_unit.set(4usize, 1u8, {
847 let cr_urx_prt_en: u32 = unsafe { ::core::mem::transmute(cr_urx_prt_en) };
848 cr_urx_prt_en as u64
849 });
850 __bindgen_bitfield_unit.set(5usize, 1u8, {
851 let cr_urx_prt_sel: u32 = unsafe { ::core::mem::transmute(cr_urx_prt_sel) };
852 cr_urx_prt_sel as u64
853 });
854 __bindgen_bitfield_unit.set(6usize, 1u8, {
855 let cr_urx_ir_en: u32 = unsafe { ::core::mem::transmute(cr_urx_ir_en) };
856 cr_urx_ir_en as u64
857 });
858 __bindgen_bitfield_unit.set(7usize, 1u8, {
859 let cr_urx_ir_inv: u32 = unsafe { ::core::mem::transmute(cr_urx_ir_inv) };
860 cr_urx_ir_inv as u64
861 });
862 __bindgen_bitfield_unit.set(8usize, 3u8, {
863 let cr_urx_bit_cnt_d: u32 = unsafe { ::core::mem::transmute(cr_urx_bit_cnt_d) };
864 cr_urx_bit_cnt_d as u64
865 });
866 __bindgen_bitfield_unit.set(11usize, 1u8, {
867 let cr_urx_deg_en: u32 = unsafe { ::core::mem::transmute(cr_urx_deg_en) };
868 cr_urx_deg_en as u64
869 });
870 __bindgen_bitfield_unit.set(12usize, 4u8, {
871 let cr_urx_deg_cnt: u32 = unsafe { ::core::mem::transmute(cr_urx_deg_cnt) };
872 cr_urx_deg_cnt as u64
873 });
874 __bindgen_bitfield_unit.set(16usize, 16u8, {
875 let cr_urx_len: u32 = unsafe { ::core::mem::transmute(cr_urx_len) };
876 cr_urx_len as u64
877 });
878 __bindgen_bitfield_unit
879 }
880}
881impl Default for uart_reg__bindgen_ty_2 {
882 fn default() -> Self {
883 unsafe { ::core::mem::zeroed() }
884 }
885}
886#[repr(C)]
887#[derive(Copy, Clone)]
888pub union uart_reg__bindgen_ty_3 {
889 pub BF: uart_reg__bindgen_ty_3__bindgen_ty_1,
890 pub WORD: u32,
891}
892#[repr(C)]
893#[repr(align(4))]
894#[derive(Default, Copy, Clone)]
895pub struct uart_reg__bindgen_ty_3__bindgen_ty_1 {
896 pub _bitfield_align_1: [u16; 0],
897 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
898}
899impl uart_reg__bindgen_ty_3__bindgen_ty_1 {
900 #[inline]
901 pub fn cr_utx_bit_prd(&self) -> u32 {
902 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
903 }
904 #[inline]
905 pub fn set_cr_utx_bit_prd(&mut self, val: u32) {
906 unsafe {
907 let val: u32 = ::core::mem::transmute(val);
908 self._bitfield_1.set(0usize, 16u8, val as u64)
909 }
910 }
911 #[inline]
912 pub fn cr_urx_bit_prd(&self) -> u32 {
913 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
914 }
915 #[inline]
916 pub fn set_cr_urx_bit_prd(&mut self, val: u32) {
917 unsafe {
918 let val: u32 = ::core::mem::transmute(val);
919 self._bitfield_1.set(16usize, 16u8, val as u64)
920 }
921 }
922 #[inline]
923 pub fn new_bitfield_1(
924 cr_utx_bit_prd: u32,
925 cr_urx_bit_prd: u32,
926 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
927 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
928 __bindgen_bitfield_unit.set(0usize, 16u8, {
929 let cr_utx_bit_prd: u32 = unsafe { ::core::mem::transmute(cr_utx_bit_prd) };
930 cr_utx_bit_prd as u64
931 });
932 __bindgen_bitfield_unit.set(16usize, 16u8, {
933 let cr_urx_bit_prd: u32 = unsafe { ::core::mem::transmute(cr_urx_bit_prd) };
934 cr_urx_bit_prd as u64
935 });
936 __bindgen_bitfield_unit
937 }
938}
939impl Default for uart_reg__bindgen_ty_3 {
940 fn default() -> Self {
941 unsafe { ::core::mem::zeroed() }
942 }
943}
944#[repr(C)]
945#[derive(Copy, Clone)]
946pub union uart_reg__bindgen_ty_4 {
947 pub BF: uart_reg__bindgen_ty_4__bindgen_ty_1,
948 pub WORD: u32,
949}
950#[repr(C)]
951#[repr(align(4))]
952#[derive(Default, Copy, Clone)]
953pub struct uart_reg__bindgen_ty_4__bindgen_ty_1 {
954 pub _bitfield_align_1: [u32; 0],
955 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
956}
957impl uart_reg__bindgen_ty_4__bindgen_ty_1 {
958 #[inline]
959 pub fn cr_uart_bit_inv(&self) -> u32 {
960 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
961 }
962 #[inline]
963 pub fn set_cr_uart_bit_inv(&mut self, val: u32) {
964 unsafe {
965 let val: u32 = ::core::mem::transmute(val);
966 self._bitfield_1.set(0usize, 1u8, val as u64)
967 }
968 }
969 #[inline]
970 pub fn reserved_1_31(&self) -> u32 {
971 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 31u8) as u32) }
972 }
973 #[inline]
974 pub fn set_reserved_1_31(&mut self, val: u32) {
975 unsafe {
976 let val: u32 = ::core::mem::transmute(val);
977 self._bitfield_1.set(1usize, 31u8, val as u64)
978 }
979 }
980 #[inline]
981 pub fn new_bitfield_1(
982 cr_uart_bit_inv: u32,
983 reserved_1_31: u32,
984 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
985 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
986 __bindgen_bitfield_unit.set(0usize, 1u8, {
987 let cr_uart_bit_inv: u32 = unsafe { ::core::mem::transmute(cr_uart_bit_inv) };
988 cr_uart_bit_inv as u64
989 });
990 __bindgen_bitfield_unit.set(1usize, 31u8, {
991 let reserved_1_31: u32 = unsafe { ::core::mem::transmute(reserved_1_31) };
992 reserved_1_31 as u64
993 });
994 __bindgen_bitfield_unit
995 }
996}
997impl Default for uart_reg__bindgen_ty_4 {
998 fn default() -> Self {
999 unsafe { ::core::mem::zeroed() }
1000 }
1001}
1002#[repr(C)]
1003#[derive(Copy, Clone)]
1004pub union uart_reg__bindgen_ty_5 {
1005 pub BF: uart_reg__bindgen_ty_5__bindgen_ty_1,
1006 pub WORD: u32,
1007}
1008#[repr(C)]
1009#[repr(align(4))]
1010#[derive(Default, Copy, Clone)]
1011pub struct uart_reg__bindgen_ty_5__bindgen_ty_1 {
1012 pub _bitfield_align_1: [u16; 0],
1013 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1014}
1015impl uart_reg__bindgen_ty_5__bindgen_ty_1 {
1016 #[inline]
1017 pub fn cr_utx_ir_pos_s(&self) -> u32 {
1018 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
1019 }
1020 #[inline]
1021 pub fn set_cr_utx_ir_pos_s(&mut self, val: u32) {
1022 unsafe {
1023 let val: u32 = ::core::mem::transmute(val);
1024 self._bitfield_1.set(0usize, 16u8, val as u64)
1025 }
1026 }
1027 #[inline]
1028 pub fn cr_utx_ir_pos_p(&self) -> u32 {
1029 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
1030 }
1031 #[inline]
1032 pub fn set_cr_utx_ir_pos_p(&mut self, val: u32) {
1033 unsafe {
1034 let val: u32 = ::core::mem::transmute(val);
1035 self._bitfield_1.set(16usize, 16u8, val as u64)
1036 }
1037 }
1038 #[inline]
1039 pub fn new_bitfield_1(
1040 cr_utx_ir_pos_s: u32,
1041 cr_utx_ir_pos_p: u32,
1042 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1043 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1044 __bindgen_bitfield_unit.set(0usize, 16u8, {
1045 let cr_utx_ir_pos_s: u32 = unsafe { ::core::mem::transmute(cr_utx_ir_pos_s) };
1046 cr_utx_ir_pos_s as u64
1047 });
1048 __bindgen_bitfield_unit.set(16usize, 16u8, {
1049 let cr_utx_ir_pos_p: u32 = unsafe { ::core::mem::transmute(cr_utx_ir_pos_p) };
1050 cr_utx_ir_pos_p as u64
1051 });
1052 __bindgen_bitfield_unit
1053 }
1054}
1055impl Default for uart_reg__bindgen_ty_5 {
1056 fn default() -> Self {
1057 unsafe { ::core::mem::zeroed() }
1058 }
1059}
1060#[repr(C)]
1061#[derive(Copy, Clone)]
1062pub union uart_reg__bindgen_ty_6 {
1063 pub BF: uart_reg__bindgen_ty_6__bindgen_ty_1,
1064 pub WORD: u32,
1065}
1066#[repr(C)]
1067#[repr(align(4))]
1068#[derive(Default, Copy, Clone)]
1069pub struct uart_reg__bindgen_ty_6__bindgen_ty_1 {
1070 pub _bitfield_align_1: [u16; 0],
1071 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1072}
1073impl uart_reg__bindgen_ty_6__bindgen_ty_1 {
1074 #[inline]
1075 pub fn cr_urx_ir_pos_s(&self) -> u32 {
1076 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
1077 }
1078 #[inline]
1079 pub fn set_cr_urx_ir_pos_s(&mut self, val: u32) {
1080 unsafe {
1081 let val: u32 = ::core::mem::transmute(val);
1082 self._bitfield_1.set(0usize, 16u8, val as u64)
1083 }
1084 }
1085 #[inline]
1086 pub fn reserved_16_31(&self) -> u32 {
1087 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
1088 }
1089 #[inline]
1090 pub fn set_reserved_16_31(&mut self, val: u32) {
1091 unsafe {
1092 let val: u32 = ::core::mem::transmute(val);
1093 self._bitfield_1.set(16usize, 16u8, val as u64)
1094 }
1095 }
1096 #[inline]
1097 pub fn new_bitfield_1(
1098 cr_urx_ir_pos_s: u32,
1099 reserved_16_31: u32,
1100 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1101 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1102 __bindgen_bitfield_unit.set(0usize, 16u8, {
1103 let cr_urx_ir_pos_s: u32 = unsafe { ::core::mem::transmute(cr_urx_ir_pos_s) };
1104 cr_urx_ir_pos_s as u64
1105 });
1106 __bindgen_bitfield_unit.set(16usize, 16u8, {
1107 let reserved_16_31: u32 = unsafe { ::core::mem::transmute(reserved_16_31) };
1108 reserved_16_31 as u64
1109 });
1110 __bindgen_bitfield_unit
1111 }
1112}
1113impl Default for uart_reg__bindgen_ty_6 {
1114 fn default() -> Self {
1115 unsafe { ::core::mem::zeroed() }
1116 }
1117}
1118#[repr(C)]
1119#[derive(Copy, Clone)]
1120pub union uart_reg__bindgen_ty_7 {
1121 pub BF: uart_reg__bindgen_ty_7__bindgen_ty_1,
1122 pub WORD: u32,
1123}
1124#[repr(C)]
1125#[repr(align(4))]
1126#[derive(Default, Copy, Clone)]
1127pub struct uart_reg__bindgen_ty_7__bindgen_ty_1 {
1128 pub _bitfield_align_1: [u32; 0],
1129 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1130}
1131impl uart_reg__bindgen_ty_7__bindgen_ty_1 {
1132 #[inline]
1133 pub fn cr_urx_rto_value(&self) -> u32 {
1134 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
1135 }
1136 #[inline]
1137 pub fn set_cr_urx_rto_value(&mut self, val: u32) {
1138 unsafe {
1139 let val: u32 = ::core::mem::transmute(val);
1140 self._bitfield_1.set(0usize, 8u8, val as u64)
1141 }
1142 }
1143 #[inline]
1144 pub fn reserved_8_31(&self) -> u32 {
1145 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
1146 }
1147 #[inline]
1148 pub fn set_reserved_8_31(&mut self, val: u32) {
1149 unsafe {
1150 let val: u32 = ::core::mem::transmute(val);
1151 self._bitfield_1.set(8usize, 24u8, val as u64)
1152 }
1153 }
1154 #[inline]
1155 pub fn new_bitfield_1(
1156 cr_urx_rto_value: u32,
1157 reserved_8_31: u32,
1158 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1159 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1160 __bindgen_bitfield_unit.set(0usize, 8u8, {
1161 let cr_urx_rto_value: u32 = unsafe { ::core::mem::transmute(cr_urx_rto_value) };
1162 cr_urx_rto_value as u64
1163 });
1164 __bindgen_bitfield_unit.set(8usize, 24u8, {
1165 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
1166 reserved_8_31 as u64
1167 });
1168 __bindgen_bitfield_unit
1169 }
1170}
1171impl Default for uart_reg__bindgen_ty_7 {
1172 fn default() -> Self {
1173 unsafe { ::core::mem::zeroed() }
1174 }
1175}
1176#[repr(C)]
1177#[derive(Copy, Clone)]
1178pub union uart_reg__bindgen_ty_8 {
1179 pub BF: uart_reg__bindgen_ty_8__bindgen_ty_1,
1180 pub WORD: u32,
1181}
1182#[repr(C)]
1183#[repr(align(4))]
1184#[derive(Default, Copy, Clone)]
1185pub struct uart_reg__bindgen_ty_8__bindgen_ty_1 {
1186 pub _bitfield_align_1: [u32; 0],
1187 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1188}
1189impl uart_reg__bindgen_ty_8__bindgen_ty_1 {
1190 #[inline]
1191 pub fn utx_end_int(&self) -> u32 {
1192 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
1193 }
1194 #[inline]
1195 pub fn set_utx_end_int(&mut self, val: u32) {
1196 unsafe {
1197 let val: u32 = ::core::mem::transmute(val);
1198 self._bitfield_1.set(0usize, 1u8, val as u64)
1199 }
1200 }
1201 #[inline]
1202 pub fn urx_end_int(&self) -> u32 {
1203 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
1204 }
1205 #[inline]
1206 pub fn set_urx_end_int(&mut self, val: u32) {
1207 unsafe {
1208 let val: u32 = ::core::mem::transmute(val);
1209 self._bitfield_1.set(1usize, 1u8, val as u64)
1210 }
1211 }
1212 #[inline]
1213 pub fn utx_fifo_int(&self) -> u32 {
1214 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
1215 }
1216 #[inline]
1217 pub fn set_utx_fifo_int(&mut self, val: u32) {
1218 unsafe {
1219 let val: u32 = ::core::mem::transmute(val);
1220 self._bitfield_1.set(2usize, 1u8, val as u64)
1221 }
1222 }
1223 #[inline]
1224 pub fn urx_fifo_int(&self) -> u32 {
1225 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
1226 }
1227 #[inline]
1228 pub fn set_urx_fifo_int(&mut self, val: u32) {
1229 unsafe {
1230 let val: u32 = ::core::mem::transmute(val);
1231 self._bitfield_1.set(3usize, 1u8, val as u64)
1232 }
1233 }
1234 #[inline]
1235 pub fn urx_rto_int(&self) -> u32 {
1236 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
1237 }
1238 #[inline]
1239 pub fn set_urx_rto_int(&mut self, val: u32) {
1240 unsafe {
1241 let val: u32 = ::core::mem::transmute(val);
1242 self._bitfield_1.set(4usize, 1u8, val as u64)
1243 }
1244 }
1245 #[inline]
1246 pub fn urx_pce_int(&self) -> u32 {
1247 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
1248 }
1249 #[inline]
1250 pub fn set_urx_pce_int(&mut self, val: u32) {
1251 unsafe {
1252 let val: u32 = ::core::mem::transmute(val);
1253 self._bitfield_1.set(5usize, 1u8, val as u64)
1254 }
1255 }
1256 #[inline]
1257 pub fn utx_fer_int(&self) -> u32 {
1258 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
1259 }
1260 #[inline]
1261 pub fn set_utx_fer_int(&mut self, val: u32) {
1262 unsafe {
1263 let val: u32 = ::core::mem::transmute(val);
1264 self._bitfield_1.set(6usize, 1u8, val as u64)
1265 }
1266 }
1267 #[inline]
1268 pub fn urx_fer_int(&self) -> u32 {
1269 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
1270 }
1271 #[inline]
1272 pub fn set_urx_fer_int(&mut self, val: u32) {
1273 unsafe {
1274 let val: u32 = ::core::mem::transmute(val);
1275 self._bitfield_1.set(7usize, 1u8, val as u64)
1276 }
1277 }
1278 #[inline]
1279 pub fn reserved_8_31(&self) -> u32 {
1280 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
1281 }
1282 #[inline]
1283 pub fn set_reserved_8_31(&mut self, val: u32) {
1284 unsafe {
1285 let val: u32 = ::core::mem::transmute(val);
1286 self._bitfield_1.set(8usize, 24u8, val as u64)
1287 }
1288 }
1289 #[inline]
1290 pub fn new_bitfield_1(
1291 utx_end_int: u32,
1292 urx_end_int: u32,
1293 utx_fifo_int: u32,
1294 urx_fifo_int: u32,
1295 urx_rto_int: u32,
1296 urx_pce_int: u32,
1297 utx_fer_int: u32,
1298 urx_fer_int: u32,
1299 reserved_8_31: u32,
1300 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1301 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1302 __bindgen_bitfield_unit.set(0usize, 1u8, {
1303 let utx_end_int: u32 = unsafe { ::core::mem::transmute(utx_end_int) };
1304 utx_end_int as u64
1305 });
1306 __bindgen_bitfield_unit.set(1usize, 1u8, {
1307 let urx_end_int: u32 = unsafe { ::core::mem::transmute(urx_end_int) };
1308 urx_end_int as u64
1309 });
1310 __bindgen_bitfield_unit.set(2usize, 1u8, {
1311 let utx_fifo_int: u32 = unsafe { ::core::mem::transmute(utx_fifo_int) };
1312 utx_fifo_int as u64
1313 });
1314 __bindgen_bitfield_unit.set(3usize, 1u8, {
1315 let urx_fifo_int: u32 = unsafe { ::core::mem::transmute(urx_fifo_int) };
1316 urx_fifo_int as u64
1317 });
1318 __bindgen_bitfield_unit.set(4usize, 1u8, {
1319 let urx_rto_int: u32 = unsafe { ::core::mem::transmute(urx_rto_int) };
1320 urx_rto_int as u64
1321 });
1322 __bindgen_bitfield_unit.set(5usize, 1u8, {
1323 let urx_pce_int: u32 = unsafe { ::core::mem::transmute(urx_pce_int) };
1324 urx_pce_int as u64
1325 });
1326 __bindgen_bitfield_unit.set(6usize, 1u8, {
1327 let utx_fer_int: u32 = unsafe { ::core::mem::transmute(utx_fer_int) };
1328 utx_fer_int as u64
1329 });
1330 __bindgen_bitfield_unit.set(7usize, 1u8, {
1331 let urx_fer_int: u32 = unsafe { ::core::mem::transmute(urx_fer_int) };
1332 urx_fer_int as u64
1333 });
1334 __bindgen_bitfield_unit.set(8usize, 24u8, {
1335 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
1336 reserved_8_31 as u64
1337 });
1338 __bindgen_bitfield_unit
1339 }
1340}
1341impl Default for uart_reg__bindgen_ty_8 {
1342 fn default() -> Self {
1343 unsafe { ::core::mem::zeroed() }
1344 }
1345}
1346#[repr(C)]
1347#[derive(Copy, Clone)]
1348pub union uart_reg__bindgen_ty_9 {
1349 pub BF: uart_reg__bindgen_ty_9__bindgen_ty_1,
1350 pub WORD: u32,
1351}
1352#[repr(C)]
1353#[repr(align(4))]
1354#[derive(Default, Copy, Clone)]
1355pub struct uart_reg__bindgen_ty_9__bindgen_ty_1 {
1356 pub _bitfield_align_1: [u32; 0],
1357 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1358}
1359impl uart_reg__bindgen_ty_9__bindgen_ty_1 {
1360 #[inline]
1361 pub fn cr_utx_end_mask(&self) -> u32 {
1362 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
1363 }
1364 #[inline]
1365 pub fn set_cr_utx_end_mask(&mut self, val: u32) {
1366 unsafe {
1367 let val: u32 = ::core::mem::transmute(val);
1368 self._bitfield_1.set(0usize, 1u8, val as u64)
1369 }
1370 }
1371 #[inline]
1372 pub fn cr_urx_end_mask(&self) -> u32 {
1373 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
1374 }
1375 #[inline]
1376 pub fn set_cr_urx_end_mask(&mut self, val: u32) {
1377 unsafe {
1378 let val: u32 = ::core::mem::transmute(val);
1379 self._bitfield_1.set(1usize, 1u8, val as u64)
1380 }
1381 }
1382 #[inline]
1383 pub fn cr_utx_fifo_mask(&self) -> u32 {
1384 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
1385 }
1386 #[inline]
1387 pub fn set_cr_utx_fifo_mask(&mut self, val: u32) {
1388 unsafe {
1389 let val: u32 = ::core::mem::transmute(val);
1390 self._bitfield_1.set(2usize, 1u8, val as u64)
1391 }
1392 }
1393 #[inline]
1394 pub fn cr_urx_fifo_mask(&self) -> u32 {
1395 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
1396 }
1397 #[inline]
1398 pub fn set_cr_urx_fifo_mask(&mut self, val: u32) {
1399 unsafe {
1400 let val: u32 = ::core::mem::transmute(val);
1401 self._bitfield_1.set(3usize, 1u8, val as u64)
1402 }
1403 }
1404 #[inline]
1405 pub fn cr_urx_rto_mask(&self) -> u32 {
1406 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
1407 }
1408 #[inline]
1409 pub fn set_cr_urx_rto_mask(&mut self, val: u32) {
1410 unsafe {
1411 let val: u32 = ::core::mem::transmute(val);
1412 self._bitfield_1.set(4usize, 1u8, val as u64)
1413 }
1414 }
1415 #[inline]
1416 pub fn cr_urx_pce_mask(&self) -> u32 {
1417 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
1418 }
1419 #[inline]
1420 pub fn set_cr_urx_pce_mask(&mut self, val: u32) {
1421 unsafe {
1422 let val: u32 = ::core::mem::transmute(val);
1423 self._bitfield_1.set(5usize, 1u8, val as u64)
1424 }
1425 }
1426 #[inline]
1427 pub fn cr_utx_fer_mask(&self) -> u32 {
1428 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
1429 }
1430 #[inline]
1431 pub fn set_cr_utx_fer_mask(&mut self, val: u32) {
1432 unsafe {
1433 let val: u32 = ::core::mem::transmute(val);
1434 self._bitfield_1.set(6usize, 1u8, val as u64)
1435 }
1436 }
1437 #[inline]
1438 pub fn cr_urx_fer_mask(&self) -> u32 {
1439 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
1440 }
1441 #[inline]
1442 pub fn set_cr_urx_fer_mask(&mut self, val: u32) {
1443 unsafe {
1444 let val: u32 = ::core::mem::transmute(val);
1445 self._bitfield_1.set(7usize, 1u8, val as u64)
1446 }
1447 }
1448 #[inline]
1449 pub fn reserved_8_31(&self) -> u32 {
1450 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
1451 }
1452 #[inline]
1453 pub fn set_reserved_8_31(&mut self, val: u32) {
1454 unsafe {
1455 let val: u32 = ::core::mem::transmute(val);
1456 self._bitfield_1.set(8usize, 24u8, val as u64)
1457 }
1458 }
1459 #[inline]
1460 pub fn new_bitfield_1(
1461 cr_utx_end_mask: u32,
1462 cr_urx_end_mask: u32,
1463 cr_utx_fifo_mask: u32,
1464 cr_urx_fifo_mask: u32,
1465 cr_urx_rto_mask: u32,
1466 cr_urx_pce_mask: u32,
1467 cr_utx_fer_mask: u32,
1468 cr_urx_fer_mask: u32,
1469 reserved_8_31: u32,
1470 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1471 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1472 __bindgen_bitfield_unit.set(0usize, 1u8, {
1473 let cr_utx_end_mask: u32 = unsafe { ::core::mem::transmute(cr_utx_end_mask) };
1474 cr_utx_end_mask as u64
1475 });
1476 __bindgen_bitfield_unit.set(1usize, 1u8, {
1477 let cr_urx_end_mask: u32 = unsafe { ::core::mem::transmute(cr_urx_end_mask) };
1478 cr_urx_end_mask as u64
1479 });
1480 __bindgen_bitfield_unit.set(2usize, 1u8, {
1481 let cr_utx_fifo_mask: u32 = unsafe { ::core::mem::transmute(cr_utx_fifo_mask) };
1482 cr_utx_fifo_mask as u64
1483 });
1484 __bindgen_bitfield_unit.set(3usize, 1u8, {
1485 let cr_urx_fifo_mask: u32 = unsafe { ::core::mem::transmute(cr_urx_fifo_mask) };
1486 cr_urx_fifo_mask as u64
1487 });
1488 __bindgen_bitfield_unit.set(4usize, 1u8, {
1489 let cr_urx_rto_mask: u32 = unsafe { ::core::mem::transmute(cr_urx_rto_mask) };
1490 cr_urx_rto_mask as u64
1491 });
1492 __bindgen_bitfield_unit.set(5usize, 1u8, {
1493 let cr_urx_pce_mask: u32 = unsafe { ::core::mem::transmute(cr_urx_pce_mask) };
1494 cr_urx_pce_mask as u64
1495 });
1496 __bindgen_bitfield_unit.set(6usize, 1u8, {
1497 let cr_utx_fer_mask: u32 = unsafe { ::core::mem::transmute(cr_utx_fer_mask) };
1498 cr_utx_fer_mask as u64
1499 });
1500 __bindgen_bitfield_unit.set(7usize, 1u8, {
1501 let cr_urx_fer_mask: u32 = unsafe { ::core::mem::transmute(cr_urx_fer_mask) };
1502 cr_urx_fer_mask as u64
1503 });
1504 __bindgen_bitfield_unit.set(8usize, 24u8, {
1505 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
1506 reserved_8_31 as u64
1507 });
1508 __bindgen_bitfield_unit
1509 }
1510}
1511impl Default for uart_reg__bindgen_ty_9 {
1512 fn default() -> Self {
1513 unsafe { ::core::mem::zeroed() }
1514 }
1515}
1516#[repr(C)]
1517#[derive(Copy, Clone)]
1518pub union uart_reg__bindgen_ty_10 {
1519 pub BF: uart_reg__bindgen_ty_10__bindgen_ty_1,
1520 pub WORD: u32,
1521}
1522#[repr(C)]
1523#[repr(align(4))]
1524#[derive(Default, Copy, Clone)]
1525pub struct uart_reg__bindgen_ty_10__bindgen_ty_1 {
1526 pub _bitfield_align_1: [u32; 0],
1527 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1528}
1529impl uart_reg__bindgen_ty_10__bindgen_ty_1 {
1530 #[inline]
1531 pub fn cr_utx_end_clr(&self) -> u32 {
1532 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
1533 }
1534 #[inline]
1535 pub fn set_cr_utx_end_clr(&mut self, val: u32) {
1536 unsafe {
1537 let val: u32 = ::core::mem::transmute(val);
1538 self._bitfield_1.set(0usize, 1u8, val as u64)
1539 }
1540 }
1541 #[inline]
1542 pub fn cr_urx_end_clr(&self) -> u32 {
1543 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
1544 }
1545 #[inline]
1546 pub fn set_cr_urx_end_clr(&mut self, val: u32) {
1547 unsafe {
1548 let val: u32 = ::core::mem::transmute(val);
1549 self._bitfield_1.set(1usize, 1u8, val as u64)
1550 }
1551 }
1552 #[inline]
1553 pub fn rsvd_2(&self) -> u32 {
1554 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
1555 }
1556 #[inline]
1557 pub fn set_rsvd_2(&mut self, val: u32) {
1558 unsafe {
1559 let val: u32 = ::core::mem::transmute(val);
1560 self._bitfield_1.set(2usize, 1u8, val as u64)
1561 }
1562 }
1563 #[inline]
1564 pub fn rsvd_3(&self) -> u32 {
1565 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
1566 }
1567 #[inline]
1568 pub fn set_rsvd_3(&mut self, val: u32) {
1569 unsafe {
1570 let val: u32 = ::core::mem::transmute(val);
1571 self._bitfield_1.set(3usize, 1u8, val as u64)
1572 }
1573 }
1574 #[inline]
1575 pub fn cr_urx_rto_clr(&self) -> u32 {
1576 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
1577 }
1578 #[inline]
1579 pub fn set_cr_urx_rto_clr(&mut self, val: u32) {
1580 unsafe {
1581 let val: u32 = ::core::mem::transmute(val);
1582 self._bitfield_1.set(4usize, 1u8, val as u64)
1583 }
1584 }
1585 #[inline]
1586 pub fn cr_urx_pce_clr(&self) -> u32 {
1587 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
1588 }
1589 #[inline]
1590 pub fn set_cr_urx_pce_clr(&mut self, val: u32) {
1591 unsafe {
1592 let val: u32 = ::core::mem::transmute(val);
1593 self._bitfield_1.set(5usize, 1u8, val as u64)
1594 }
1595 }
1596 #[inline]
1597 pub fn rsvd_6(&self) -> u32 {
1598 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
1599 }
1600 #[inline]
1601 pub fn set_rsvd_6(&mut self, val: u32) {
1602 unsafe {
1603 let val: u32 = ::core::mem::transmute(val);
1604 self._bitfield_1.set(6usize, 1u8, val as u64)
1605 }
1606 }
1607 #[inline]
1608 pub fn rsvd_7(&self) -> u32 {
1609 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
1610 }
1611 #[inline]
1612 pub fn set_rsvd_7(&mut self, val: u32) {
1613 unsafe {
1614 let val: u32 = ::core::mem::transmute(val);
1615 self._bitfield_1.set(7usize, 1u8, val as u64)
1616 }
1617 }
1618 #[inline]
1619 pub fn reserved_8_31(&self) -> u32 {
1620 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
1621 }
1622 #[inline]
1623 pub fn set_reserved_8_31(&mut self, val: u32) {
1624 unsafe {
1625 let val: u32 = ::core::mem::transmute(val);
1626 self._bitfield_1.set(8usize, 24u8, val as u64)
1627 }
1628 }
1629 #[inline]
1630 pub fn new_bitfield_1(
1631 cr_utx_end_clr: u32,
1632 cr_urx_end_clr: u32,
1633 rsvd_2: u32,
1634 rsvd_3: u32,
1635 cr_urx_rto_clr: u32,
1636 cr_urx_pce_clr: u32,
1637 rsvd_6: u32,
1638 rsvd_7: u32,
1639 reserved_8_31: u32,
1640 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1641 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1642 __bindgen_bitfield_unit.set(0usize, 1u8, {
1643 let cr_utx_end_clr: u32 = unsafe { ::core::mem::transmute(cr_utx_end_clr) };
1644 cr_utx_end_clr as u64
1645 });
1646 __bindgen_bitfield_unit.set(1usize, 1u8, {
1647 let cr_urx_end_clr: u32 = unsafe { ::core::mem::transmute(cr_urx_end_clr) };
1648 cr_urx_end_clr as u64
1649 });
1650 __bindgen_bitfield_unit.set(2usize, 1u8, {
1651 let rsvd_2: u32 = unsafe { ::core::mem::transmute(rsvd_2) };
1652 rsvd_2 as u64
1653 });
1654 __bindgen_bitfield_unit.set(3usize, 1u8, {
1655 let rsvd_3: u32 = unsafe { ::core::mem::transmute(rsvd_3) };
1656 rsvd_3 as u64
1657 });
1658 __bindgen_bitfield_unit.set(4usize, 1u8, {
1659 let cr_urx_rto_clr: u32 = unsafe { ::core::mem::transmute(cr_urx_rto_clr) };
1660 cr_urx_rto_clr as u64
1661 });
1662 __bindgen_bitfield_unit.set(5usize, 1u8, {
1663 let cr_urx_pce_clr: u32 = unsafe { ::core::mem::transmute(cr_urx_pce_clr) };
1664 cr_urx_pce_clr as u64
1665 });
1666 __bindgen_bitfield_unit.set(6usize, 1u8, {
1667 let rsvd_6: u32 = unsafe { ::core::mem::transmute(rsvd_6) };
1668 rsvd_6 as u64
1669 });
1670 __bindgen_bitfield_unit.set(7usize, 1u8, {
1671 let rsvd_7: u32 = unsafe { ::core::mem::transmute(rsvd_7) };
1672 rsvd_7 as u64
1673 });
1674 __bindgen_bitfield_unit.set(8usize, 24u8, {
1675 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
1676 reserved_8_31 as u64
1677 });
1678 __bindgen_bitfield_unit
1679 }
1680}
1681impl Default for uart_reg__bindgen_ty_10 {
1682 fn default() -> Self {
1683 unsafe { ::core::mem::zeroed() }
1684 }
1685}
1686#[repr(C)]
1687#[derive(Copy, Clone)]
1688pub union uart_reg__bindgen_ty_11 {
1689 pub BF: uart_reg__bindgen_ty_11__bindgen_ty_1,
1690 pub WORD: u32,
1691}
1692#[repr(C)]
1693#[repr(align(4))]
1694#[derive(Default, Copy, Clone)]
1695pub struct uart_reg__bindgen_ty_11__bindgen_ty_1 {
1696 pub _bitfield_align_1: [u32; 0],
1697 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1698}
1699impl uart_reg__bindgen_ty_11__bindgen_ty_1 {
1700 #[inline]
1701 pub fn cr_utx_end_en(&self) -> u32 {
1702 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
1703 }
1704 #[inline]
1705 pub fn set_cr_utx_end_en(&mut self, val: u32) {
1706 unsafe {
1707 let val: u32 = ::core::mem::transmute(val);
1708 self._bitfield_1.set(0usize, 1u8, val as u64)
1709 }
1710 }
1711 #[inline]
1712 pub fn cr_urx_end_en(&self) -> u32 {
1713 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
1714 }
1715 #[inline]
1716 pub fn set_cr_urx_end_en(&mut self, val: u32) {
1717 unsafe {
1718 let val: u32 = ::core::mem::transmute(val);
1719 self._bitfield_1.set(1usize, 1u8, val as u64)
1720 }
1721 }
1722 #[inline]
1723 pub fn cr_utx_fifo_en(&self) -> u32 {
1724 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
1725 }
1726 #[inline]
1727 pub fn set_cr_utx_fifo_en(&mut self, val: u32) {
1728 unsafe {
1729 let val: u32 = ::core::mem::transmute(val);
1730 self._bitfield_1.set(2usize, 1u8, val as u64)
1731 }
1732 }
1733 #[inline]
1734 pub fn cr_urx_fifo_en(&self) -> u32 {
1735 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
1736 }
1737 #[inline]
1738 pub fn set_cr_urx_fifo_en(&mut self, val: u32) {
1739 unsafe {
1740 let val: u32 = ::core::mem::transmute(val);
1741 self._bitfield_1.set(3usize, 1u8, val as u64)
1742 }
1743 }
1744 #[inline]
1745 pub fn cr_urx_rto_en(&self) -> u32 {
1746 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
1747 }
1748 #[inline]
1749 pub fn set_cr_urx_rto_en(&mut self, val: u32) {
1750 unsafe {
1751 let val: u32 = ::core::mem::transmute(val);
1752 self._bitfield_1.set(4usize, 1u8, val as u64)
1753 }
1754 }
1755 #[inline]
1756 pub fn cr_urx_pce_en(&self) -> u32 {
1757 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
1758 }
1759 #[inline]
1760 pub fn set_cr_urx_pce_en(&mut self, val: u32) {
1761 unsafe {
1762 let val: u32 = ::core::mem::transmute(val);
1763 self._bitfield_1.set(5usize, 1u8, val as u64)
1764 }
1765 }
1766 #[inline]
1767 pub fn cr_utx_fer_en(&self) -> u32 {
1768 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
1769 }
1770 #[inline]
1771 pub fn set_cr_utx_fer_en(&mut self, val: u32) {
1772 unsafe {
1773 let val: u32 = ::core::mem::transmute(val);
1774 self._bitfield_1.set(6usize, 1u8, val as u64)
1775 }
1776 }
1777 #[inline]
1778 pub fn cr_urx_fer_en(&self) -> u32 {
1779 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
1780 }
1781 #[inline]
1782 pub fn set_cr_urx_fer_en(&mut self, val: u32) {
1783 unsafe {
1784 let val: u32 = ::core::mem::transmute(val);
1785 self._bitfield_1.set(7usize, 1u8, val as u64)
1786 }
1787 }
1788 #[inline]
1789 pub fn reserved_8_31(&self) -> u32 {
1790 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
1791 }
1792 #[inline]
1793 pub fn set_reserved_8_31(&mut self, val: u32) {
1794 unsafe {
1795 let val: u32 = ::core::mem::transmute(val);
1796 self._bitfield_1.set(8usize, 24u8, val as u64)
1797 }
1798 }
1799 #[inline]
1800 pub fn new_bitfield_1(
1801 cr_utx_end_en: u32,
1802 cr_urx_end_en: u32,
1803 cr_utx_fifo_en: u32,
1804 cr_urx_fifo_en: u32,
1805 cr_urx_rto_en: u32,
1806 cr_urx_pce_en: u32,
1807 cr_utx_fer_en: u32,
1808 cr_urx_fer_en: u32,
1809 reserved_8_31: u32,
1810 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1811 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1812 __bindgen_bitfield_unit.set(0usize, 1u8, {
1813 let cr_utx_end_en: u32 = unsafe { ::core::mem::transmute(cr_utx_end_en) };
1814 cr_utx_end_en as u64
1815 });
1816 __bindgen_bitfield_unit.set(1usize, 1u8, {
1817 let cr_urx_end_en: u32 = unsafe { ::core::mem::transmute(cr_urx_end_en) };
1818 cr_urx_end_en as u64
1819 });
1820 __bindgen_bitfield_unit.set(2usize, 1u8, {
1821 let cr_utx_fifo_en: u32 = unsafe { ::core::mem::transmute(cr_utx_fifo_en) };
1822 cr_utx_fifo_en as u64
1823 });
1824 __bindgen_bitfield_unit.set(3usize, 1u8, {
1825 let cr_urx_fifo_en: u32 = unsafe { ::core::mem::transmute(cr_urx_fifo_en) };
1826 cr_urx_fifo_en as u64
1827 });
1828 __bindgen_bitfield_unit.set(4usize, 1u8, {
1829 let cr_urx_rto_en: u32 = unsafe { ::core::mem::transmute(cr_urx_rto_en) };
1830 cr_urx_rto_en as u64
1831 });
1832 __bindgen_bitfield_unit.set(5usize, 1u8, {
1833 let cr_urx_pce_en: u32 = unsafe { ::core::mem::transmute(cr_urx_pce_en) };
1834 cr_urx_pce_en as u64
1835 });
1836 __bindgen_bitfield_unit.set(6usize, 1u8, {
1837 let cr_utx_fer_en: u32 = unsafe { ::core::mem::transmute(cr_utx_fer_en) };
1838 cr_utx_fer_en as u64
1839 });
1840 __bindgen_bitfield_unit.set(7usize, 1u8, {
1841 let cr_urx_fer_en: u32 = unsafe { ::core::mem::transmute(cr_urx_fer_en) };
1842 cr_urx_fer_en as u64
1843 });
1844 __bindgen_bitfield_unit.set(8usize, 24u8, {
1845 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
1846 reserved_8_31 as u64
1847 });
1848 __bindgen_bitfield_unit
1849 }
1850}
1851impl Default for uart_reg__bindgen_ty_11 {
1852 fn default() -> Self {
1853 unsafe { ::core::mem::zeroed() }
1854 }
1855}
1856#[repr(C)]
1857#[derive(Copy, Clone)]
1858pub union uart_reg__bindgen_ty_12 {
1859 pub BF: uart_reg__bindgen_ty_12__bindgen_ty_1,
1860 pub WORD: u32,
1861}
1862#[repr(C)]
1863#[repr(align(4))]
1864#[derive(Default, Copy, Clone)]
1865pub struct uart_reg__bindgen_ty_12__bindgen_ty_1 {
1866 pub _bitfield_align_1: [u32; 0],
1867 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1868}
1869impl uart_reg__bindgen_ty_12__bindgen_ty_1 {
1870 #[inline]
1871 pub fn sts_utx_bus_busy(&self) -> u32 {
1872 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
1873 }
1874 #[inline]
1875 pub fn set_sts_utx_bus_busy(&mut self, val: u32) {
1876 unsafe {
1877 let val: u32 = ::core::mem::transmute(val);
1878 self._bitfield_1.set(0usize, 1u8, val as u64)
1879 }
1880 }
1881 #[inline]
1882 pub fn sts_urx_bus_busy(&self) -> u32 {
1883 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
1884 }
1885 #[inline]
1886 pub fn set_sts_urx_bus_busy(&mut self, val: u32) {
1887 unsafe {
1888 let val: u32 = ::core::mem::transmute(val);
1889 self._bitfield_1.set(1usize, 1u8, val as u64)
1890 }
1891 }
1892 #[inline]
1893 pub fn reserved_2_31(&self) -> u32 {
1894 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 30u8) as u32) }
1895 }
1896 #[inline]
1897 pub fn set_reserved_2_31(&mut self, val: u32) {
1898 unsafe {
1899 let val: u32 = ::core::mem::transmute(val);
1900 self._bitfield_1.set(2usize, 30u8, val as u64)
1901 }
1902 }
1903 #[inline]
1904 pub fn new_bitfield_1(
1905 sts_utx_bus_busy: u32,
1906 sts_urx_bus_busy: u32,
1907 reserved_2_31: u32,
1908 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1909 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1910 __bindgen_bitfield_unit.set(0usize, 1u8, {
1911 let sts_utx_bus_busy: u32 = unsafe { ::core::mem::transmute(sts_utx_bus_busy) };
1912 sts_utx_bus_busy as u64
1913 });
1914 __bindgen_bitfield_unit.set(1usize, 1u8, {
1915 let sts_urx_bus_busy: u32 = unsafe { ::core::mem::transmute(sts_urx_bus_busy) };
1916 sts_urx_bus_busy as u64
1917 });
1918 __bindgen_bitfield_unit.set(2usize, 30u8, {
1919 let reserved_2_31: u32 = unsafe { ::core::mem::transmute(reserved_2_31) };
1920 reserved_2_31 as u64
1921 });
1922 __bindgen_bitfield_unit
1923 }
1924}
1925impl Default for uart_reg__bindgen_ty_12 {
1926 fn default() -> Self {
1927 unsafe { ::core::mem::zeroed() }
1928 }
1929}
1930#[repr(C)]
1931#[derive(Copy, Clone)]
1932pub union uart_reg__bindgen_ty_13 {
1933 pub BF: uart_reg__bindgen_ty_13__bindgen_ty_1,
1934 pub WORD: u32,
1935}
1936#[repr(C)]
1937#[repr(align(4))]
1938#[derive(Default, Copy, Clone)]
1939pub struct uart_reg__bindgen_ty_13__bindgen_ty_1 {
1940 pub _bitfield_align_1: [u16; 0],
1941 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
1942}
1943impl uart_reg__bindgen_ty_13__bindgen_ty_1 {
1944 #[inline]
1945 pub fn sts_urx_abr_prd_start(&self) -> u32 {
1946 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 16u8) as u32) }
1947 }
1948 #[inline]
1949 pub fn set_sts_urx_abr_prd_start(&mut self, val: u32) {
1950 unsafe {
1951 let val: u32 = ::core::mem::transmute(val);
1952 self._bitfield_1.set(0usize, 16u8, val as u64)
1953 }
1954 }
1955 #[inline]
1956 pub fn sts_urx_abr_prd_0x55(&self) -> u32 {
1957 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 16u8) as u32) }
1958 }
1959 #[inline]
1960 pub fn set_sts_urx_abr_prd_0x55(&mut self, val: u32) {
1961 unsafe {
1962 let val: u32 = ::core::mem::transmute(val);
1963 self._bitfield_1.set(16usize, 16u8, val as u64)
1964 }
1965 }
1966 #[inline]
1967 pub fn new_bitfield_1(
1968 sts_urx_abr_prd_start: u32,
1969 sts_urx_abr_prd_0x55: u32,
1970 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
1971 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
1972 __bindgen_bitfield_unit.set(0usize, 16u8, {
1973 let sts_urx_abr_prd_start: u32 =
1974 unsafe { ::core::mem::transmute(sts_urx_abr_prd_start) };
1975 sts_urx_abr_prd_start as u64
1976 });
1977 __bindgen_bitfield_unit.set(16usize, 16u8, {
1978 let sts_urx_abr_prd_0x55: u32 = unsafe { ::core::mem::transmute(sts_urx_abr_prd_0x55) };
1979 sts_urx_abr_prd_0x55 as u64
1980 });
1981 __bindgen_bitfield_unit
1982 }
1983}
1984impl Default for uart_reg__bindgen_ty_13 {
1985 fn default() -> Self {
1986 unsafe { ::core::mem::zeroed() }
1987 }
1988}
1989#[repr(C)]
1990#[derive(Copy, Clone)]
1991pub union uart_reg__bindgen_ty_14 {
1992 pub BF: uart_reg__bindgen_ty_14__bindgen_ty_1,
1993 pub WORD: u32,
1994}
1995#[repr(C)]
1996#[repr(align(4))]
1997#[derive(Default, Copy, Clone)]
1998pub struct uart_reg__bindgen_ty_14__bindgen_ty_1 {
1999 pub _bitfield_align_1: [u32; 0],
2000 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
2001}
2002impl uart_reg__bindgen_ty_14__bindgen_ty_1 {
2003 #[inline]
2004 pub fn uart_dma_tx_en(&self) -> u32 {
2005 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 1u8) as u32) }
2006 }
2007 #[inline]
2008 pub fn set_uart_dma_tx_en(&mut self, val: u32) {
2009 unsafe {
2010 let val: u32 = ::core::mem::transmute(val);
2011 self._bitfield_1.set(0usize, 1u8, val as u64)
2012 }
2013 }
2014 #[inline]
2015 pub fn uart_dma_rx_en(&self) -> u32 {
2016 unsafe { ::core::mem::transmute(self._bitfield_1.get(1usize, 1u8) as u32) }
2017 }
2018 #[inline]
2019 pub fn set_uart_dma_rx_en(&mut self, val: u32) {
2020 unsafe {
2021 let val: u32 = ::core::mem::transmute(val);
2022 self._bitfield_1.set(1usize, 1u8, val as u64)
2023 }
2024 }
2025 #[inline]
2026 pub fn tx_fifo_clr(&self) -> u32 {
2027 unsafe { ::core::mem::transmute(self._bitfield_1.get(2usize, 1u8) as u32) }
2028 }
2029 #[inline]
2030 pub fn set_tx_fifo_clr(&mut self, val: u32) {
2031 unsafe {
2032 let val: u32 = ::core::mem::transmute(val);
2033 self._bitfield_1.set(2usize, 1u8, val as u64)
2034 }
2035 }
2036 #[inline]
2037 pub fn rx_fifo_clr(&self) -> u32 {
2038 unsafe { ::core::mem::transmute(self._bitfield_1.get(3usize, 1u8) as u32) }
2039 }
2040 #[inline]
2041 pub fn set_rx_fifo_clr(&mut self, val: u32) {
2042 unsafe {
2043 let val: u32 = ::core::mem::transmute(val);
2044 self._bitfield_1.set(3usize, 1u8, val as u64)
2045 }
2046 }
2047 #[inline]
2048 pub fn tx_fifo_overflow(&self) -> u32 {
2049 unsafe { ::core::mem::transmute(self._bitfield_1.get(4usize, 1u8) as u32) }
2050 }
2051 #[inline]
2052 pub fn set_tx_fifo_overflow(&mut self, val: u32) {
2053 unsafe {
2054 let val: u32 = ::core::mem::transmute(val);
2055 self._bitfield_1.set(4usize, 1u8, val as u64)
2056 }
2057 }
2058 #[inline]
2059 pub fn tx_fifo_underflow(&self) -> u32 {
2060 unsafe { ::core::mem::transmute(self._bitfield_1.get(5usize, 1u8) as u32) }
2061 }
2062 #[inline]
2063 pub fn set_tx_fifo_underflow(&mut self, val: u32) {
2064 unsafe {
2065 let val: u32 = ::core::mem::transmute(val);
2066 self._bitfield_1.set(5usize, 1u8, val as u64)
2067 }
2068 }
2069 #[inline]
2070 pub fn rx_fifo_overflow(&self) -> u32 {
2071 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 1u8) as u32) }
2072 }
2073 #[inline]
2074 pub fn set_rx_fifo_overflow(&mut self, val: u32) {
2075 unsafe {
2076 let val: u32 = ::core::mem::transmute(val);
2077 self._bitfield_1.set(6usize, 1u8, val as u64)
2078 }
2079 }
2080 #[inline]
2081 pub fn rx_fifo_underflow(&self) -> u32 {
2082 unsafe { ::core::mem::transmute(self._bitfield_1.get(7usize, 1u8) as u32) }
2083 }
2084 #[inline]
2085 pub fn set_rx_fifo_underflow(&mut self, val: u32) {
2086 unsafe {
2087 let val: u32 = ::core::mem::transmute(val);
2088 self._bitfield_1.set(7usize, 1u8, val as u64)
2089 }
2090 }
2091 #[inline]
2092 pub fn reserved_8_31(&self) -> u32 {
2093 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
2094 }
2095 #[inline]
2096 pub fn set_reserved_8_31(&mut self, val: u32) {
2097 unsafe {
2098 let val: u32 = ::core::mem::transmute(val);
2099 self._bitfield_1.set(8usize, 24u8, val as u64)
2100 }
2101 }
2102 #[inline]
2103 pub fn new_bitfield_1(
2104 uart_dma_tx_en: u32,
2105 uart_dma_rx_en: u32,
2106 tx_fifo_clr: u32,
2107 rx_fifo_clr: u32,
2108 tx_fifo_overflow: u32,
2109 tx_fifo_underflow: u32,
2110 rx_fifo_overflow: u32,
2111 rx_fifo_underflow: u32,
2112 reserved_8_31: u32,
2113 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
2114 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
2115 __bindgen_bitfield_unit.set(0usize, 1u8, {
2116 let uart_dma_tx_en: u32 = unsafe { ::core::mem::transmute(uart_dma_tx_en) };
2117 uart_dma_tx_en as u64
2118 });
2119 __bindgen_bitfield_unit.set(1usize, 1u8, {
2120 let uart_dma_rx_en: u32 = unsafe { ::core::mem::transmute(uart_dma_rx_en) };
2121 uart_dma_rx_en as u64
2122 });
2123 __bindgen_bitfield_unit.set(2usize, 1u8, {
2124 let tx_fifo_clr: u32 = unsafe { ::core::mem::transmute(tx_fifo_clr) };
2125 tx_fifo_clr as u64
2126 });
2127 __bindgen_bitfield_unit.set(3usize, 1u8, {
2128 let rx_fifo_clr: u32 = unsafe { ::core::mem::transmute(rx_fifo_clr) };
2129 rx_fifo_clr as u64
2130 });
2131 __bindgen_bitfield_unit.set(4usize, 1u8, {
2132 let tx_fifo_overflow: u32 = unsafe { ::core::mem::transmute(tx_fifo_overflow) };
2133 tx_fifo_overflow as u64
2134 });
2135 __bindgen_bitfield_unit.set(5usize, 1u8, {
2136 let tx_fifo_underflow: u32 = unsafe { ::core::mem::transmute(tx_fifo_underflow) };
2137 tx_fifo_underflow as u64
2138 });
2139 __bindgen_bitfield_unit.set(6usize, 1u8, {
2140 let rx_fifo_overflow: u32 = unsafe { ::core::mem::transmute(rx_fifo_overflow) };
2141 rx_fifo_overflow as u64
2142 });
2143 __bindgen_bitfield_unit.set(7usize, 1u8, {
2144 let rx_fifo_underflow: u32 = unsafe { ::core::mem::transmute(rx_fifo_underflow) };
2145 rx_fifo_underflow as u64
2146 });
2147 __bindgen_bitfield_unit.set(8usize, 24u8, {
2148 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
2149 reserved_8_31 as u64
2150 });
2151 __bindgen_bitfield_unit
2152 }
2153}
2154impl Default for uart_reg__bindgen_ty_14 {
2155 fn default() -> Self {
2156 unsafe { ::core::mem::zeroed() }
2157 }
2158}
2159#[repr(C)]
2160#[derive(Copy, Clone)]
2161pub union uart_reg__bindgen_ty_15 {
2162 pub BF: uart_reg__bindgen_ty_15__bindgen_ty_1,
2163 pub WORD: u32,
2164}
2165#[repr(C)]
2166#[repr(align(4))]
2167#[derive(Default, Copy, Clone)]
2168pub struct uart_reg__bindgen_ty_15__bindgen_ty_1 {
2169 pub _bitfield_align_1: [u8; 0],
2170 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
2171}
2172impl uart_reg__bindgen_ty_15__bindgen_ty_1 {
2173 #[inline]
2174 pub fn tx_fifo_cnt(&self) -> u32 {
2175 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 6u8) as u32) }
2176 }
2177 #[inline]
2178 pub fn set_tx_fifo_cnt(&mut self, val: u32) {
2179 unsafe {
2180 let val: u32 = ::core::mem::transmute(val);
2181 self._bitfield_1.set(0usize, 6u8, val as u64)
2182 }
2183 }
2184 #[inline]
2185 pub fn reserved_6_7(&self) -> u32 {
2186 unsafe { ::core::mem::transmute(self._bitfield_1.get(6usize, 2u8) as u32) }
2187 }
2188 #[inline]
2189 pub fn set_reserved_6_7(&mut self, val: u32) {
2190 unsafe {
2191 let val: u32 = ::core::mem::transmute(val);
2192 self._bitfield_1.set(6usize, 2u8, val as u64)
2193 }
2194 }
2195 #[inline]
2196 pub fn rx_fifo_cnt(&self) -> u32 {
2197 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 6u8) as u32) }
2198 }
2199 #[inline]
2200 pub fn set_rx_fifo_cnt(&mut self, val: u32) {
2201 unsafe {
2202 let val: u32 = ::core::mem::transmute(val);
2203 self._bitfield_1.set(8usize, 6u8, val as u64)
2204 }
2205 }
2206 #[inline]
2207 pub fn reserved_14_15(&self) -> u32 {
2208 unsafe { ::core::mem::transmute(self._bitfield_1.get(14usize, 2u8) as u32) }
2209 }
2210 #[inline]
2211 pub fn set_reserved_14_15(&mut self, val: u32) {
2212 unsafe {
2213 let val: u32 = ::core::mem::transmute(val);
2214 self._bitfield_1.set(14usize, 2u8, val as u64)
2215 }
2216 }
2217 #[inline]
2218 pub fn tx_fifo_th(&self) -> u32 {
2219 unsafe { ::core::mem::transmute(self._bitfield_1.get(16usize, 5u8) as u32) }
2220 }
2221 #[inline]
2222 pub fn set_tx_fifo_th(&mut self, val: u32) {
2223 unsafe {
2224 let val: u32 = ::core::mem::transmute(val);
2225 self._bitfield_1.set(16usize, 5u8, val as u64)
2226 }
2227 }
2228 #[inline]
2229 pub fn reserved_21_23(&self) -> u32 {
2230 unsafe { ::core::mem::transmute(self._bitfield_1.get(21usize, 3u8) as u32) }
2231 }
2232 #[inline]
2233 pub fn set_reserved_21_23(&mut self, val: u32) {
2234 unsafe {
2235 let val: u32 = ::core::mem::transmute(val);
2236 self._bitfield_1.set(21usize, 3u8, val as u64)
2237 }
2238 }
2239 #[inline]
2240 pub fn rx_fifo_th(&self) -> u32 {
2241 unsafe { ::core::mem::transmute(self._bitfield_1.get(24usize, 5u8) as u32) }
2242 }
2243 #[inline]
2244 pub fn set_rx_fifo_th(&mut self, val: u32) {
2245 unsafe {
2246 let val: u32 = ::core::mem::transmute(val);
2247 self._bitfield_1.set(24usize, 5u8, val as u64)
2248 }
2249 }
2250 #[inline]
2251 pub fn reserved_29_31(&self) -> u32 {
2252 unsafe { ::core::mem::transmute(self._bitfield_1.get(29usize, 3u8) as u32) }
2253 }
2254 #[inline]
2255 pub fn set_reserved_29_31(&mut self, val: u32) {
2256 unsafe {
2257 let val: u32 = ::core::mem::transmute(val);
2258 self._bitfield_1.set(29usize, 3u8, val as u64)
2259 }
2260 }
2261 #[inline]
2262 pub fn new_bitfield_1(
2263 tx_fifo_cnt: u32,
2264 reserved_6_7: u32,
2265 rx_fifo_cnt: u32,
2266 reserved_14_15: u32,
2267 tx_fifo_th: u32,
2268 reserved_21_23: u32,
2269 rx_fifo_th: u32,
2270 reserved_29_31: u32,
2271 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
2272 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
2273 __bindgen_bitfield_unit.set(0usize, 6u8, {
2274 let tx_fifo_cnt: u32 = unsafe { ::core::mem::transmute(tx_fifo_cnt) };
2275 tx_fifo_cnt as u64
2276 });
2277 __bindgen_bitfield_unit.set(6usize, 2u8, {
2278 let reserved_6_7: u32 = unsafe { ::core::mem::transmute(reserved_6_7) };
2279 reserved_6_7 as u64
2280 });
2281 __bindgen_bitfield_unit.set(8usize, 6u8, {
2282 let rx_fifo_cnt: u32 = unsafe { ::core::mem::transmute(rx_fifo_cnt) };
2283 rx_fifo_cnt as u64
2284 });
2285 __bindgen_bitfield_unit.set(14usize, 2u8, {
2286 let reserved_14_15: u32 = unsafe { ::core::mem::transmute(reserved_14_15) };
2287 reserved_14_15 as u64
2288 });
2289 __bindgen_bitfield_unit.set(16usize, 5u8, {
2290 let tx_fifo_th: u32 = unsafe { ::core::mem::transmute(tx_fifo_th) };
2291 tx_fifo_th as u64
2292 });
2293 __bindgen_bitfield_unit.set(21usize, 3u8, {
2294 let reserved_21_23: u32 = unsafe { ::core::mem::transmute(reserved_21_23) };
2295 reserved_21_23 as u64
2296 });
2297 __bindgen_bitfield_unit.set(24usize, 5u8, {
2298 let rx_fifo_th: u32 = unsafe { ::core::mem::transmute(rx_fifo_th) };
2299 rx_fifo_th as u64
2300 });
2301 __bindgen_bitfield_unit.set(29usize, 3u8, {
2302 let reserved_29_31: u32 = unsafe { ::core::mem::transmute(reserved_29_31) };
2303 reserved_29_31 as u64
2304 });
2305 __bindgen_bitfield_unit
2306 }
2307}
2308impl Default for uart_reg__bindgen_ty_15 {
2309 fn default() -> Self {
2310 unsafe { ::core::mem::zeroed() }
2311 }
2312}
2313#[repr(C)]
2314#[derive(Copy, Clone)]
2315pub union uart_reg__bindgen_ty_16 {
2316 pub BF: uart_reg__bindgen_ty_16__bindgen_ty_1,
2317 pub WORD: u32,
2318}
2319#[repr(C)]
2320#[repr(align(4))]
2321#[derive(Default, Copy, Clone)]
2322pub struct uart_reg__bindgen_ty_16__bindgen_ty_1 {
2323 pub _bitfield_align_1: [u32; 0],
2324 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
2325}
2326impl uart_reg__bindgen_ty_16__bindgen_ty_1 {
2327 #[inline]
2328 pub fn uart_fifo_wdata(&self) -> u32 {
2329 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
2330 }
2331 #[inline]
2332 pub fn set_uart_fifo_wdata(&mut self, val: u32) {
2333 unsafe {
2334 let val: u32 = ::core::mem::transmute(val);
2335 self._bitfield_1.set(0usize, 8u8, val as u64)
2336 }
2337 }
2338 #[inline]
2339 pub fn reserved_8_31(&self) -> u32 {
2340 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
2341 }
2342 #[inline]
2343 pub fn set_reserved_8_31(&mut self, val: u32) {
2344 unsafe {
2345 let val: u32 = ::core::mem::transmute(val);
2346 self._bitfield_1.set(8usize, 24u8, val as u64)
2347 }
2348 }
2349 #[inline]
2350 pub fn new_bitfield_1(
2351 uart_fifo_wdata: u32,
2352 reserved_8_31: u32,
2353 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
2354 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
2355 __bindgen_bitfield_unit.set(0usize, 8u8, {
2356 let uart_fifo_wdata: u32 = unsafe { ::core::mem::transmute(uart_fifo_wdata) };
2357 uart_fifo_wdata as u64
2358 });
2359 __bindgen_bitfield_unit.set(8usize, 24u8, {
2360 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
2361 reserved_8_31 as u64
2362 });
2363 __bindgen_bitfield_unit
2364 }
2365}
2366impl Default for uart_reg__bindgen_ty_16 {
2367 fn default() -> Self {
2368 unsafe { ::core::mem::zeroed() }
2369 }
2370}
2371#[repr(C)]
2372#[derive(Copy, Clone)]
2373pub union uart_reg__bindgen_ty_17 {
2374 pub BF: uart_reg__bindgen_ty_17__bindgen_ty_1,
2375 pub WORD: u32,
2376}
2377#[repr(C)]
2378#[repr(align(4))]
2379#[derive(Default, Copy, Clone)]
2380pub struct uart_reg__bindgen_ty_17__bindgen_ty_1 {
2381 pub _bitfield_align_1: [u32; 0],
2382 pub _bitfield_1: __BindgenBitfieldUnit<[u8; 4usize]>,
2383}
2384impl uart_reg__bindgen_ty_17__bindgen_ty_1 {
2385 #[inline]
2386 pub fn uart_fifo_rdata(&self) -> u32 {
2387 unsafe { ::core::mem::transmute(self._bitfield_1.get(0usize, 8u8) as u32) }
2388 }
2389 #[inline]
2390 pub fn set_uart_fifo_rdata(&mut self, val: u32) {
2391 unsafe {
2392 let val: u32 = ::core::mem::transmute(val);
2393 self._bitfield_1.set(0usize, 8u8, val as u64)
2394 }
2395 }
2396 #[inline]
2397 pub fn reserved_8_31(&self) -> u32 {
2398 unsafe { ::core::mem::transmute(self._bitfield_1.get(8usize, 24u8) as u32) }
2399 }
2400 #[inline]
2401 pub fn set_reserved_8_31(&mut self, val: u32) {
2402 unsafe {
2403 let val: u32 = ::core::mem::transmute(val);
2404 self._bitfield_1.set(8usize, 24u8, val as u64)
2405 }
2406 }
2407 #[inline]
2408 pub fn new_bitfield_1(
2409 uart_fifo_rdata: u32,
2410 reserved_8_31: u32,
2411 ) -> __BindgenBitfieldUnit<[u8; 4usize]> {
2412 let mut __bindgen_bitfield_unit: __BindgenBitfieldUnit<[u8; 4usize]> = Default::default();
2413 __bindgen_bitfield_unit.set(0usize, 8u8, {
2414 let uart_fifo_rdata: u32 = unsafe { ::core::mem::transmute(uart_fifo_rdata) };
2415 uart_fifo_rdata as u64
2416 });
2417 __bindgen_bitfield_unit.set(8usize, 24u8, {
2418 let reserved_8_31: u32 = unsafe { ::core::mem::transmute(reserved_8_31) };
2419 reserved_8_31 as u64
2420 });
2421 __bindgen_bitfield_unit
2422 }
2423}
2424impl Default for uart_reg__bindgen_ty_17 {
2425 fn default() -> Self {
2426 unsafe { ::core::mem::zeroed() }
2427 }
2428}
2429impl Default for uart_reg {
2430 fn default() -> Self {
2431 unsafe { ::core::mem::zeroed() }
2432 }
2433}
2434pub type uart_reg_t = uart_reg;
2435pub const BL_Err_Type_SUCCESS: BL_Err_Type = 0;
2436pub const BL_Err_Type_ERROR: BL_Err_Type = 1;
2437pub const BL_Err_Type_TIMEOUT: BL_Err_Type = 2;
2438#[doc = " @brief Error type definition"]
2439pub type BL_Err_Type = ::cty::c_uint;
2440pub const BL_Fun_Type_DISABLE: BL_Fun_Type = 0;
2441pub const BL_Fun_Type_ENABLE: BL_Fun_Type = 1;
2442#[doc = " @brief Functional type definition"]
2443pub type BL_Fun_Type = ::cty::c_uint;
2444pub const BL_Sts_Type_RESET: BL_Sts_Type = 0;
2445pub const BL_Sts_Type_SET: BL_Sts_Type = 1;
2446#[doc = " @brief Status type definition"]
2447pub type BL_Sts_Type = ::cty::c_uint;
2448pub const BL_Mask_Type_UNMASK: BL_Mask_Type = 0;
2449pub const BL_Mask_Type_MASK: BL_Mask_Type = 1;
2450#[doc = " @brief Mask type definition"]
2451pub type BL_Mask_Type = ::cty::c_uint;
2452#[doc = " @brief Interrupt callback function type"]
2453pub type intCallback_Type = ::core::option::Option<unsafe extern "C" fn()>;
2454#[doc = "< UART0 port define"]
2455pub const UART_ID_Type_UART0_ID: UART_ID_Type = 0;
2456#[doc = "< UART1 port define"]
2457pub const UART_ID_Type_UART1_ID: UART_ID_Type = 1;
2458#[doc = "< UART MAX ID define"]
2459pub const UART_ID_Type_UART_ID_MAX: UART_ID_Type = 2;
2460#[doc = " @brief UART port type definition"]
2461pub type UART_ID_Type = ::cty::c_uint;
2462#[doc = "< UART TX Direction"]
2463pub const UART_Direction_Type_UART_TX: UART_Direction_Type = 0;
2464#[doc = "< UART RX Direction"]
2465pub const UART_Direction_Type_UART_RX: UART_Direction_Type = 1;
2466#[doc = "< UART TX and RX Direction"]
2467pub const UART_Direction_Type_UART_TXRX: UART_Direction_Type = 2;
2468#[doc = " @brief UART direction type definition"]
2469pub type UART_Direction_Type = ::cty::c_uint;
2470#[doc = "< UART parity none define"]
2471pub const UART_Parity_Type_UART_PARITY_NONE: UART_Parity_Type = 0;
2472#[doc = "< UART parity odd define"]
2473pub const UART_Parity_Type_UART_PARITY_ODD: UART_Parity_Type = 1;
2474#[doc = "< UART parity even define"]
2475pub const UART_Parity_Type_UART_PARITY_EVEN: UART_Parity_Type = 2;
2476#[doc = " @brief UART parity type definition"]
2477pub type UART_Parity_Type = ::cty::c_uint;
2478#[doc = "< UART data bits length:5 bits"]
2479pub const UART_DataBits_Type_UART_DATABITS_5: UART_DataBits_Type = 0;
2480#[doc = "< UART data bits length:6 bits"]
2481pub const UART_DataBits_Type_UART_DATABITS_6: UART_DataBits_Type = 1;
2482#[doc = "< UART data bits length:7 bits"]
2483pub const UART_DataBits_Type_UART_DATABITS_7: UART_DataBits_Type = 2;
2484#[doc = "< UART data bits length:8 bits"]
2485pub const UART_DataBits_Type_UART_DATABITS_8: UART_DataBits_Type = 3;
2486#[doc = " @brief UART data bits type definiton"]
2487pub type UART_DataBits_Type = ::cty::c_uint;
2488#[doc = "< UART data stop bits length:1 bits"]
2489pub const UART_StopBits_Type_UART_STOPBITS_1: UART_StopBits_Type = 0;
2490#[doc = "< UART data stop bits length:1.5 bits"]
2491pub const UART_StopBits_Type_UART_STOPBITS_1_5: UART_StopBits_Type = 1;
2492#[doc = "< UART data stop bits length:2 bits"]
2493pub const UART_StopBits_Type_UART_STOPBITS_2: UART_StopBits_Type = 2;
2494#[doc = " @brief UART stop bits type definiton"]
2495pub type UART_StopBits_Type = ::cty::c_uint;
2496#[doc = "< UART each byte is send out LSB-first"]
2497pub const UART_ByteBitInverse_Type_UART_LSB_FIRST: UART_ByteBitInverse_Type = 0;
2498#[doc = "< UART each byte is send out MSB-first"]
2499pub const UART_ByteBitInverse_Type_UART_MSB_FIRST: UART_ByteBitInverse_Type = 1;
2500#[doc = " @brief UART each data byte is send out LSB-first or MSB-first type definiton"]
2501pub type UART_ByteBitInverse_Type = ::cty::c_uint;
2502#[doc = "< UART auto baudrate detection using codeword 0x55"]
2503pub const UART_AutoBaudDetection_Type_UART_AUTOBAUD_0X55: UART_AutoBaudDetection_Type = 0;
2504#[doc = "< UART auto baudrate detection using start bit"]
2505pub const UART_AutoBaudDetection_Type_UART_AUTOBAUD_STARTBIT: UART_AutoBaudDetection_Type = 1;
2506#[doc = " @brief UART auto baudrate detection using codeword 0x55 or start bit definiton"]
2507pub type UART_AutoBaudDetection_Type = ::cty::c_uint;
2508#[doc = "< UART tx transfer end interrupt"]
2509pub const UART_INT_Type_UART_INT_TX_END: UART_INT_Type = 0;
2510#[doc = "< UART rx transfer end interrupt"]
2511pub const UART_INT_Type_UART_INT_RX_END: UART_INT_Type = 1;
2512#[doc = "< UART tx fifo interrupt when tx fifo count reaches,auto clear"]
2513pub const UART_INT_Type_UART_INT_TX_FIFO_REQ: UART_INT_Type = 2;
2514#[doc = "< UART rx fifo interrupt when rx fifo count reaches,auto clear"]
2515pub const UART_INT_Type_UART_INT_RX_FIFO_REQ: UART_INT_Type = 3;
2516#[doc = "< UART rx time-out interrupt"]
2517pub const UART_INT_Type_UART_INT_RTO: UART_INT_Type = 4;
2518#[doc = "< UART rx parity check error interrupt"]
2519pub const UART_INT_Type_UART_INT_PCE: UART_INT_Type = 5;
2520#[doc = "< UART tx fifo overflow/underflow error interrupt"]
2521pub const UART_INT_Type_UART_INT_TX_FER: UART_INT_Type = 6;
2522#[doc = "< UART rx fifo overflow/underflow error interrupt"]
2523pub const UART_INT_Type_UART_INT_RX_FER: UART_INT_Type = 7;
2524#[doc = "< All the interrupt"]
2525pub const UART_INT_Type_UART_INT_ALL: UART_INT_Type = 8;
2526#[doc = " @brief UART interrupt type definition"]
2527pub type UART_INT_Type = ::cty::c_uint;
2528#[doc = "< UART tx fifo overflow"]
2529pub const UART_Overflow_Type_UART_TX_OVERFLOW: UART_Overflow_Type = 0;
2530#[doc = "< UART tx fifo underflow"]
2531pub const UART_Overflow_Type_UART_TX_UNDERFLOW: UART_Overflow_Type = 1;
2532#[doc = "< UART rx fifo overflow"]
2533pub const UART_Overflow_Type_UART_RX_OVERFLOW: UART_Overflow_Type = 2;
2534#[doc = "< UART rx fifo underflow"]
2535pub const UART_Overflow_Type_UART_RX_UNDERFLOW: UART_Overflow_Type = 3;
2536#[doc = " @brief UART overflow or underflow type definition"]
2537pub type UART_Overflow_Type = ::cty::c_uint;
2538#[doc = " @brief UART configuration structure type definition"]
2539#[repr(C)]
2540#[derive(Copy, Clone)]
2541pub struct UART_CFG_Type {
2542 #[doc = "< Uart module clock"]
2543 pub uartClk: u32,
2544 #[doc = "< Uart baudrate"]
2545 pub baudRate: u32,
2546 #[doc = "< Uart frame length of data bit"]
2547 pub dataBits: UART_DataBits_Type,
2548 #[doc = "< Uart frame length of stop bit"]
2549 pub stopBits: UART_StopBits_Type,
2550 #[doc = "< Uart parity check type"]
2551 pub parity: UART_Parity_Type,
2552 #[doc = "< Enable or disable tx CTS flow control"]
2553 pub ctsFlowControl: BL_Fun_Type,
2554 #[doc = "< Enable or disable rx input de-glitch function"]
2555 pub rxDeglitch: BL_Fun_Type,
2556 #[doc = "< Enable or disable rx RTS output SW control mode"]
2557 pub rtsSoftwareControl: BL_Fun_Type,
2558 #[doc = "< Uart each data byte is send out LSB-first or MSB-first"]
2559 pub byteBitInverse: UART_ByteBitInverse_Type,
2560}
2561impl Default for UART_CFG_Type {
2562 fn default() -> Self {
2563 unsafe { ::core::mem::zeroed() }
2564 }
2565}
2566#[doc = " @brief UART FIFO configuration structure type definition"]
2567#[repr(C)]
2568#[derive(Copy, Clone)]
2569pub struct UART_FifoCfg_Type {
2570 #[doc = "< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value"]
2571 pub txFifoDmaThreshold: u8,
2572 #[doc = "< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value"]
2573 pub rxFifoDmaThreshold: u8,
2574 #[doc = "< Enable or disable tx dma req/ack interface"]
2575 pub txFifoDmaEnable: BL_Fun_Type,
2576 #[doc = "< Enable or disable rx dma req/ack interface"]
2577 pub rxFifoDmaEnable: BL_Fun_Type,
2578}
2579impl Default for UART_FifoCfg_Type {
2580 fn default() -> Self {
2581 unsafe { ::core::mem::zeroed() }
2582 }
2583}
2584#[doc = " @brief UART infrared configuration structure type definition"]
2585#[repr(C)]
2586#[derive(Copy, Clone)]
2587pub struct UART_IrCfg_Type {
2588 #[doc = "< Enable or disable uart tx ir mode"]
2589 pub txIrEnable: BL_Fun_Type,
2590 #[doc = "< Enable or disable uart rx ir mode"]
2591 pub rxIrEnable: BL_Fun_Type,
2592 #[doc = "< Enable or disable inverse signal of uart tx output in ir mode"]
2593 pub txIrInverse: BL_Fun_Type,
2594 #[doc = "< Enable or disable inverse signal of uart rx input in ir mode"]
2595 pub rxIrInverse: BL_Fun_Type,
2596 #[doc = "< Set start position of uart tx ir pulse"]
2597 pub txIrPulseStart: u16,
2598 #[doc = "< Set stop position of uart tx ir pulse"]
2599 pub txIrPulseStop: u16,
2600 #[doc = "< Set start position of uart rx pulse recovered from ir signal"]
2601 pub rxIrPulseStart: u16,
2602}
2603impl Default for UART_IrCfg_Type {
2604 fn default() -> Self {
2605 unsafe { ::core::mem::zeroed() }
2606 }
2607}
2608#[safe_wrap(_)] extern "C" {
2609 pub fn UART_Init(uartId: UART_ID_Type, uartCfg: *mut UART_CFG_Type) -> BL_Err_Type;
2610}
2611#[safe_wrap(_)] extern "C" {
2612 pub fn UART_DeInit(uartId: UART_ID_Type) -> BL_Err_Type;
2613}
2614#[safe_wrap(_)] extern "C" {
2615 pub fn UART_FifoConfig(uartId: UART_ID_Type, fifoCfg: *mut UART_FifoCfg_Type) -> BL_Err_Type;
2616}
2617#[safe_wrap(_)] extern "C" {
2618 pub fn UART_IrConfig(uartId: UART_ID_Type, irCfg: *mut UART_IrCfg_Type) -> BL_Err_Type;
2619}
2620#[safe_wrap(_)] extern "C" {
2621 pub fn UART_Enable(uartId: UART_ID_Type, direct: UART_Direction_Type) -> BL_Err_Type;
2622}
2623#[safe_wrap(_)] extern "C" {
2624 pub fn UART_Disable(uartId: UART_ID_Type, direct: UART_Direction_Type) -> BL_Err_Type;
2625}
2626#[safe_wrap(_)] extern "C" {
2627 pub fn UART_SetTxDataLength(uartId: UART_ID_Type, length: u16) -> BL_Err_Type;
2628}
2629#[safe_wrap(_)] extern "C" {
2630 pub fn UART_SetRxDataLength(uartId: UART_ID_Type, length: u16) -> BL_Err_Type;
2631}
2632#[safe_wrap(_)] extern "C" {
2633 pub fn UART_SetRxTimeoutValue(uartId: UART_ID_Type, time: u8) -> BL_Err_Type;
2634}
2635#[safe_wrap(_)] extern "C" {
2636 pub fn UART_SetDeglitchCount(uartId: UART_ID_Type, deglitchCnt: u8) -> BL_Err_Type;
2637}
2638#[safe_wrap(_)] extern "C" {
2639 pub fn UART_SetBaudrate(
2640 uartId: UART_ID_Type,
2641 autoBaudDet: UART_AutoBaudDetection_Type,
2642 ) -> BL_Err_Type;
2643}
2644#[safe_wrap(_)] extern "C" {
2645 pub fn UART_SetRtsValue(uartId: UART_ID_Type) -> BL_Err_Type;
2646}
2647#[safe_wrap(_)] extern "C" {
2648 pub fn UART_ClrRtsValue(uartId: UART_ID_Type) -> BL_Err_Type;
2649}
2650#[safe_wrap(_)] extern "C" {
2651 pub fn UART_TxFreeRun(uartId: UART_ID_Type, txFreeRun: BL_Fun_Type) -> BL_Err_Type;
2652}
2653#[safe_wrap(_)] extern "C" {
2654 pub fn UART_AutoBaudDetection(uartId: UART_ID_Type, autoBaud: BL_Fun_Type) -> BL_Err_Type;
2655}
2656#[safe_wrap(_)] extern "C" {
2657 pub fn UART_TxFifoClear(uartId: UART_ID_Type) -> BL_Err_Type;
2658}
2659#[safe_wrap(_)] extern "C" {
2660 pub fn UART_RxFifoClear(uartId: UART_ID_Type) -> BL_Err_Type;
2661}
2662#[safe_wrap(_)] extern "C" {
2663 pub fn UART_IntMask(
2664 uartId: UART_ID_Type,
2665 intType: UART_INT_Type,
2666 intMask: BL_Mask_Type,
2667 ) -> BL_Err_Type;
2668}
2669#[safe_wrap(_)] extern "C" {
2670 pub fn UART_IntClear(uartId: UART_ID_Type, intType: UART_INT_Type) -> BL_Err_Type;
2671}
2672#[safe_wrap(_)] extern "C" {
2673 pub fn UART_Int_Callback_Install(
2674 uartId: UART_ID_Type,
2675 intType: UART_INT_Type,
2676 cbFun: intCallback_Type,
2677 ) -> BL_Err_Type;
2678}
2679#[safe_wrap(_)] extern "C" {
2680 pub fn UART_SendData(uartId: UART_ID_Type, data: *mut u8, len: u32) -> BL_Err_Type;
2681}
2682#[safe_wrap(_)] extern "C" {
2683 pub fn UART_SendDataBlock(uartId: UART_ID_Type, data: *mut u8, len: u32) -> BL_Err_Type;
2684}
2685#[safe_wrap(_)] extern "C" {
2686 pub fn UART_ReceiveData(uartId: UART_ID_Type, data: *mut u8, maxLen: u32) -> u32;
2687}
2688#[safe_wrap(_)] extern "C" {
2689 pub fn UART_GetAutoBaudCount(
2690 uartId: UART_ID_Type,
2691 autoBaudDet: UART_AutoBaudDetection_Type,
2692 ) -> u16;
2693}
2694#[safe_wrap(_)] extern "C" {
2695 pub fn UART_GetTxFifoCount(uartId: UART_ID_Type) -> u8;
2696}
2697#[safe_wrap(_)] extern "C" {
2698 pub fn UART_GetRxFifoCount(uartId: UART_ID_Type) -> u8;
2699}
2700#[safe_wrap(_)] extern "C" {
2701 pub fn UART_GetIntStatus(uartId: UART_ID_Type, intType: UART_INT_Type) -> BL_Sts_Type;
2702}
2703#[safe_wrap(_)] extern "C" {
2704 pub fn UART_GetTxBusBusyStatus(uartId: UART_ID_Type) -> BL_Sts_Type;
2705}
2706#[safe_wrap(_)] extern "C" {
2707 pub fn UART_GetRxBusBusyStatus(uartId: UART_ID_Type) -> BL_Sts_Type;
2708}
2709#[safe_wrap(_)] extern "C" {
2710 pub fn UART_GetOverflowStatus(
2711 uartId: UART_ID_Type,
2712 overflow: UART_Overflow_Type,
2713 ) -> BL_Sts_Type;
2714}
2715pub type cb_uart_notify_t = ::core::option::Option<unsafe extern "C" fn(arg: *mut ::cty::c_void)>;
2716#[safe_wrap(_)] extern "C" {
2717 pub fn bl_uart_gpio_init(
2718 id: u8,
2719 tx: u8,
2720 rx: u8,
2721 rts: u8,
2722 cts: u8,
2723 baudrate: ::cty::c_int,
2724 ) -> ::cty::c_int;
2725}
2726#[safe_wrap(_)] extern "C" {
2727 pub fn bl_uart_init(
2728 id: u8,
2729 tx_pin: u8,
2730 rx_pin: u8,
2731 cts_pin: u8,
2732 rts_pin: u8,
2733 baudrate: u32,
2734 ) -> ::cty::c_int;
2735}
2736#[safe_wrap(_)] extern "C" {
2737 pub fn bl_uart_debug_early_init(baudrate: u32) -> ::cty::c_int;
2738}
2739#[safe_wrap(_)] extern "C" {
2740 pub fn bl_uart_early_init(id: u8, tx_pin: u8, baudrate: u32) -> ::cty::c_int;
2741}
2742#[safe_wrap(_)] extern "C" {
2743 pub fn bl_uart_int_rx_enable(id: u8) -> ::cty::c_int;
2744}
2745#[safe_wrap(_)] extern "C" {
2746 pub fn bl_uart_int_rx_disable(id: u8) -> ::cty::c_int;
2747}
2748#[safe_wrap(_)] extern "C" {
2749 pub fn bl_uart_int_tx_enable(id: u8) -> ::cty::c_int;
2750}
2751#[safe_wrap(_)] extern "C" {
2752 pub fn bl_uart_int_tx_disable(id: u8) -> ::cty::c_int;
2753}
2754#[safe_wrap(_)] extern "C" {
2755 pub fn bl_uart_string_send(id: u8, data: *mut ::cty::c_char) -> ::cty::c_int;
2756}
2757#[safe_wrap(_)] extern "C" {
2758 pub fn bl_uart_flush(id: u8) -> ::cty::c_int;
2759}
2760#[safe_wrap(_)] extern "C" {
2761 pub fn bl_uart_getdefconfig(id: u8, parity: *mut u8);
2762}
2763#[safe_wrap(_)] extern "C" {
2764 pub fn bl_uart_setconfig(id: u8, baudrate: u32, parity: UART_Parity_Type);
2765}
2766#[safe_wrap(_)] extern "C" {
2767 pub fn bl_uart_setbaud(id: u8, baud: u32);
2768}
2769#[safe_wrap(_)] extern "C" {
2770 pub fn bl_uart_data_send(id: u8, data: u8) -> ::cty::c_int;
2771}
2772#[safe_wrap(_)] extern "C" {
2773 pub fn bl_uart_datas_send(id: u8, data: *mut u8, len: ::cty::c_int) -> ::cty::c_int;
2774}
2775#[safe_wrap(_)] extern "C" {
2776 pub fn bl_uart_data_recv(id: u8) -> ::cty::c_int;
2777}
2778#[safe_wrap(_)] extern "C" {
2779 pub fn bl_uart_int_enable(id: u8) -> ::cty::c_int;
2780}
2781#[safe_wrap(_)] extern "C" {
2782 pub fn bl_uart_int_disable(id: u8) -> ::cty::c_int;
2783}
2784#[safe_wrap(_)] extern "C" {
2785 pub fn bl_uart_int_rx_notify_register(
2786 id: u8,
2787 cb: cb_uart_notify_t,
2788 arg: *mut ::cty::c_void,
2789 ) -> ::cty::c_int;
2790}
2791#[safe_wrap(_)] extern "C" {
2792 pub fn bl_uart_int_tx_notify_register(
2793 id: u8,
2794 cb: cb_uart_notify_t,
2795 arg: *mut ::cty::c_void,
2796 ) -> ::cty::c_int;
2797}
2798#[safe_wrap(_)] extern "C" {
2799 pub fn bl_uart_int_rx_notify_unregister(
2800 id: u8,
2801 cb: cb_uart_notify_t,
2802 arg: *mut ::cty::c_void,
2803 ) -> ::cty::c_int;
2804}
2805#[safe_wrap(_)] extern "C" {
2806 pub fn bl_uart_int_tx_notify_unregister(
2807 id: u8,
2808 cb: cb_uart_notify_t,
2809 arg: *mut ::cty::c_void,
2810 ) -> ::cty::c_int;
2811}