bl602_pac/uart/
uart_int_en.rs

1#[doc = "Register `uart_int_en` reader"]
2pub struct R(crate::R<UART_INT_EN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_INT_EN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_INT_EN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_INT_EN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_int_en` writer"]
17pub struct W(crate::W<UART_INT_EN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_INT_EN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_INT_EN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_INT_EN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `cr_utx_end_en` reader - "]
38pub type CR_UTX_END_EN_R = crate::BitReader<bool>;
39#[doc = "Field `cr_utx_end_en` writer - "]
40pub type CR_UTX_END_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
41#[doc = "Field `cr_urx_end_en` reader - "]
42pub type CR_URX_END_EN_R = crate::BitReader<bool>;
43#[doc = "Field `cr_urx_end_en` writer - "]
44pub type CR_URX_END_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
45#[doc = "Field `cr_utx_fifo_en` reader - "]
46pub type CR_UTX_FIFO_EN_R = crate::BitReader<bool>;
47#[doc = "Field `cr_utx_fifo_en` writer - "]
48pub type CR_UTX_FIFO_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
49#[doc = "Field `cr_urx_fifo_en` reader - "]
50pub type CR_URX_FIFO_EN_R = crate::BitReader<bool>;
51#[doc = "Field `cr_urx_fifo_en` writer - "]
52pub type CR_URX_FIFO_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
53#[doc = "Field `cr_urx_rto_en` reader - "]
54pub type CR_URX_RTO_EN_R = crate::BitReader<bool>;
55#[doc = "Field `cr_urx_rto_en` writer - "]
56pub type CR_URX_RTO_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
57#[doc = "Field `cr_urx_pce_en` reader - "]
58pub type CR_URX_PCE_EN_R = crate::BitReader<bool>;
59#[doc = "Field `cr_urx_pce_en` writer - "]
60pub type CR_URX_PCE_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
61#[doc = "Field `cr_utx_fer_en` reader - "]
62pub type CR_UTX_FER_EN_R = crate::BitReader<bool>;
63#[doc = "Field `cr_utx_fer_en` writer - "]
64pub type CR_UTX_FER_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
65#[doc = "Field `cr_urx_fer_en` reader - "]
66pub type CR_URX_FER_EN_R = crate::BitReader<bool>;
67#[doc = "Field `cr_urx_fer_en` writer - "]
68pub type CR_URX_FER_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, UART_INT_EN_SPEC, bool, O>;
69impl R {
70    #[doc = "Bit 0"]
71    #[inline(always)]
72    pub fn cr_utx_end_en(&self) -> CR_UTX_END_EN_R {
73        CR_UTX_END_EN_R::new((self.bits & 1) != 0)
74    }
75    #[doc = "Bit 1"]
76    #[inline(always)]
77    pub fn cr_urx_end_en(&self) -> CR_URX_END_EN_R {
78        CR_URX_END_EN_R::new(((self.bits >> 1) & 1) != 0)
79    }
80    #[doc = "Bit 2"]
81    #[inline(always)]
82    pub fn cr_utx_fifo_en(&self) -> CR_UTX_FIFO_EN_R {
83        CR_UTX_FIFO_EN_R::new(((self.bits >> 2) & 1) != 0)
84    }
85    #[doc = "Bit 3"]
86    #[inline(always)]
87    pub fn cr_urx_fifo_en(&self) -> CR_URX_FIFO_EN_R {
88        CR_URX_FIFO_EN_R::new(((self.bits >> 3) & 1) != 0)
89    }
90    #[doc = "Bit 4"]
91    #[inline(always)]
92    pub fn cr_urx_rto_en(&self) -> CR_URX_RTO_EN_R {
93        CR_URX_RTO_EN_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5"]
96    #[inline(always)]
97    pub fn cr_urx_pce_en(&self) -> CR_URX_PCE_EN_R {
98        CR_URX_PCE_EN_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 6"]
101    #[inline(always)]
102    pub fn cr_utx_fer_en(&self) -> CR_UTX_FER_EN_R {
103        CR_UTX_FER_EN_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 7"]
106    #[inline(always)]
107    pub fn cr_urx_fer_en(&self) -> CR_URX_FER_EN_R {
108        CR_URX_FER_EN_R::new(((self.bits >> 7) & 1) != 0)
109    }
110}
111impl W {
112    #[doc = "Bit 0"]
113    #[inline(always)]
114    #[must_use]
115    pub fn cr_utx_end_en(&mut self) -> CR_UTX_END_EN_W<0> {
116        CR_UTX_END_EN_W::new(self)
117    }
118    #[doc = "Bit 1"]
119    #[inline(always)]
120    #[must_use]
121    pub fn cr_urx_end_en(&mut self) -> CR_URX_END_EN_W<1> {
122        CR_URX_END_EN_W::new(self)
123    }
124    #[doc = "Bit 2"]
125    #[inline(always)]
126    #[must_use]
127    pub fn cr_utx_fifo_en(&mut self) -> CR_UTX_FIFO_EN_W<2> {
128        CR_UTX_FIFO_EN_W::new(self)
129    }
130    #[doc = "Bit 3"]
131    #[inline(always)]
132    #[must_use]
133    pub fn cr_urx_fifo_en(&mut self) -> CR_URX_FIFO_EN_W<3> {
134        CR_URX_FIFO_EN_W::new(self)
135    }
136    #[doc = "Bit 4"]
137    #[inline(always)]
138    #[must_use]
139    pub fn cr_urx_rto_en(&mut self) -> CR_URX_RTO_EN_W<4> {
140        CR_URX_RTO_EN_W::new(self)
141    }
142    #[doc = "Bit 5"]
143    #[inline(always)]
144    #[must_use]
145    pub fn cr_urx_pce_en(&mut self) -> CR_URX_PCE_EN_W<5> {
146        CR_URX_PCE_EN_W::new(self)
147    }
148    #[doc = "Bit 6"]
149    #[inline(always)]
150    #[must_use]
151    pub fn cr_utx_fer_en(&mut self) -> CR_UTX_FER_EN_W<6> {
152        CR_UTX_FER_EN_W::new(self)
153    }
154    #[doc = "Bit 7"]
155    #[inline(always)]
156    #[must_use]
157    pub fn cr_urx_fer_en(&mut self) -> CR_URX_FER_EN_W<7> {
158        CR_URX_FER_EN_W::new(self)
159    }
160    #[doc = "Writes raw bits to the register."]
161    #[inline(always)]
162    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
163        self.0.bits(bits);
164        self
165    }
166}
167#[doc = "UART interrupt enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_int_en](index.html) module"]
168pub struct UART_INT_EN_SPEC;
169impl crate::RegisterSpec for UART_INT_EN_SPEC {
170    type Ux = u32;
171}
172#[doc = "`read()` method returns [uart_int_en::R](R) reader structure"]
173impl crate::Readable for UART_INT_EN_SPEC {
174    type Reader = R;
175}
176#[doc = "`write(|w| ..)` method takes [uart_int_en::W](W) writer structure"]
177impl crate::Writable for UART_INT_EN_SPEC {
178    type Writer = W;
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets uart_int_en to value 0xff"]
183impl crate::Resettable for UART_INT_EN_SPEC {
184    const RESET_VALUE: Self::Ux = 0xff;
185}
bl602_pac/uart/uart_int_en.rs

bl602_pac/uart/
uart_int_en.rs
