bl602_pac/uart/
uart_fifo_config_0.rs

1#[doc = "Register `uart_fifo_config_0` reader"]
2pub struct R(crate::R<UART_FIFO_CONFIG_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<UART_FIFO_CONFIG_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<UART_FIFO_CONFIG_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<UART_FIFO_CONFIG_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `uart_fifo_config_0` writer"]
17pub struct W(crate::W<UART_FIFO_CONFIG_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<UART_FIFO_CONFIG_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<UART_FIFO_CONFIG_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<UART_FIFO_CONFIG_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `uart_dma_tx_en` reader - "]
38pub type UART_DMA_TX_EN_R = crate::BitReader<bool>;
39#[doc = "Field `uart_dma_tx_en` writer - "]
40pub type UART_DMA_TX_EN_W<'a, const O: u8> =
41    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
42#[doc = "Field `uart_dma_rx_en` reader - "]
43pub type UART_DMA_RX_EN_R = crate::BitReader<bool>;
44#[doc = "Field `uart_dma_rx_en` writer - "]
45pub type UART_DMA_RX_EN_W<'a, const O: u8> =
46    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
47#[doc = "Field `tx_fifo_clr` reader - "]
48pub type TX_FIFO_CLR_R = crate::BitReader<bool>;
49#[doc = "Field `tx_fifo_clr` writer - "]
50pub type TX_FIFO_CLR_W<'a, const O: u8> =
51    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
52#[doc = "Field `rx_fifo_clr` reader - "]
53pub type RX_FIFO_CLR_R = crate::BitReader<bool>;
54#[doc = "Field `rx_fifo_clr` writer - "]
55pub type RX_FIFO_CLR_W<'a, const O: u8> =
56    crate::BitWriter<'a, u32, UART_FIFO_CONFIG_0_SPEC, bool, O>;
57#[doc = "Field `tx_fifo_overflow` reader - "]
58pub type TX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
59#[doc = "Field `tx_fifo_underflow` reader - "]
60pub type TX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
61#[doc = "Field `rx_fifo_overflow` reader - "]
62pub type RX_FIFO_OVERFLOW_R = crate::BitReader<bool>;
63#[doc = "Field `rx_fifo_underflow` reader - "]
64pub type RX_FIFO_UNDERFLOW_R = crate::BitReader<bool>;
65impl R {
66    #[doc = "Bit 0"]
67    #[inline(always)]
68    pub fn uart_dma_tx_en(&self) -> UART_DMA_TX_EN_R {
69        UART_DMA_TX_EN_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1"]
72    #[inline(always)]
73    pub fn uart_dma_rx_en(&self) -> UART_DMA_RX_EN_R {
74        UART_DMA_RX_EN_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2"]
77    #[inline(always)]
78    pub fn tx_fifo_clr(&self) -> TX_FIFO_CLR_R {
79        TX_FIFO_CLR_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3"]
82    #[inline(always)]
83    pub fn rx_fifo_clr(&self) -> RX_FIFO_CLR_R {
84        RX_FIFO_CLR_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4"]
87    #[inline(always)]
88    pub fn tx_fifo_overflow(&self) -> TX_FIFO_OVERFLOW_R {
89        TX_FIFO_OVERFLOW_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5"]
92    #[inline(always)]
93    pub fn tx_fifo_underflow(&self) -> TX_FIFO_UNDERFLOW_R {
94        TX_FIFO_UNDERFLOW_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6"]
97    #[inline(always)]
98    pub fn rx_fifo_overflow(&self) -> RX_FIFO_OVERFLOW_R {
99        RX_FIFO_OVERFLOW_R::new(((self.bits >> 6) & 1) != 0)
100    }
101    #[doc = "Bit 7"]
102    #[inline(always)]
103    pub fn rx_fifo_underflow(&self) -> RX_FIFO_UNDERFLOW_R {
104        RX_FIFO_UNDERFLOW_R::new(((self.bits >> 7) & 1) != 0)
105    }
106}
107impl W {
108    #[doc = "Bit 0"]
109    #[inline(always)]
110    #[must_use]
111    pub fn uart_dma_tx_en(&mut self) -> UART_DMA_TX_EN_W<0> {
112        UART_DMA_TX_EN_W::new(self)
113    }
114    #[doc = "Bit 1"]
115    #[inline(always)]
116    #[must_use]
117    pub fn uart_dma_rx_en(&mut self) -> UART_DMA_RX_EN_W<1> {
118        UART_DMA_RX_EN_W::new(self)
119    }
120    #[doc = "Bit 2"]
121    #[inline(always)]
122    #[must_use]
123    pub fn tx_fifo_clr(&mut self) -> TX_FIFO_CLR_W<2> {
124        TX_FIFO_CLR_W::new(self)
125    }
126    #[doc = "Bit 3"]
127    #[inline(always)]
128    #[must_use]
129    pub fn rx_fifo_clr(&mut self) -> RX_FIFO_CLR_W<3> {
130        RX_FIFO_CLR_W::new(self)
131    }
132    #[doc = "Writes raw bits to the register."]
133    #[inline(always)]
134    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
135        self.0.bits(bits);
136        self
137    }
138}
139#[doc = "uart_fifo_config_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_fifo_config_0](index.html) module"]
140pub struct UART_FIFO_CONFIG_0_SPEC;
141impl crate::RegisterSpec for UART_FIFO_CONFIG_0_SPEC {
142    type Ux = u32;
143}
144#[doc = "`read()` method returns [uart_fifo_config_0::R](R) reader structure"]
145impl crate::Readable for UART_FIFO_CONFIG_0_SPEC {
146    type Reader = R;
147}
148#[doc = "`write(|w| ..)` method takes [uart_fifo_config_0::W](W) writer structure"]
149impl crate::Writable for UART_FIFO_CONFIG_0_SPEC {
150    type Writer = W;
151    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
152    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
153}
154#[doc = "`reset()` method sets uart_fifo_config_0 to value 0"]
155impl crate::Resettable for UART_FIFO_CONFIG_0_SPEC {
156    const RESET_VALUE: Self::Ux = 0;
157}
bl602_pac/uart/uart_fifo_config_0.rs

bl602_pac/uart/
uart_fifo_config_0.rs
