bl602_pac/timer/
tcvsyn2.rs

1#[doc = "Register `TCVSYN2` reader"]
2pub struct R(crate::R<TCVSYN2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<TCVSYN2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<TCVSYN2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<TCVSYN2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `tcvsyn2` reader - "]
17pub type TCVSYN2_R = crate::FieldReader<u32, u32>;
18impl R {
19    #[doc = "Bits 0:31"]
20    #[inline(always)]
21    pub fn tcvsyn2(&self) -> TCVSYN2_R {
22        TCVSYN2_R::new(self.bits)
23    }
24}
25#[doc = "TCVSYN2.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tcvsyn2](index.html) module"]
26pub struct TCVSYN2_SPEC;
27impl crate::RegisterSpec for TCVSYN2_SPEC {
28    type Ux = u32;
29}
30#[doc = "`read()` method returns [tcvsyn2::R](R) reader structure"]
31impl crate::Readable for TCVSYN2_SPEC {
32    type Reader = R;
33}
34#[doc = "`reset()` method sets TCVSYN2 to value 0"]
35impl crate::Resettable for TCVSYN2_SPEC {
36    const RESET_VALUE: Self::Ux = 0;
37}
bl602_pac/timer/tcvsyn2.rs

bl602_pac/timer/
tcvsyn2.rs
