bl602_pac/sec_eng/
se_sha_0_ctrl.rs1#[doc = "Register `se_sha_0_ctrl` reader"]
2pub struct R(crate::R<SE_SHA_0_CTRL_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SE_SHA_0_CTRL_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SE_SHA_0_CTRL_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SE_SHA_0_CTRL_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `se_sha_0_ctrl` writer"]
17pub struct W(crate::W<SE_SHA_0_CTRL_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SE_SHA_0_CTRL_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SE_SHA_0_CTRL_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SE_SHA_0_CTRL_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `se_sha_0_busy` reader - "]
38pub type SE_SHA_0_BUSY_R = crate::BitReader<bool>;
39#[doc = "Field `se_sha_0_trig_1t` reader - "]
40pub type SE_SHA_0_TRIG_1T_R = crate::BitReader<bool>;
41#[doc = "Field `se_sha_0_trig_1t` writer - "]
42pub type SE_SHA_0_TRIG_1T_W<'a, const O: u8> =
43 crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
44#[doc = "Field `se_sha_0_mode` reader - "]
45pub type SE_SHA_0_MODE_R = crate::FieldReader<u8, u8>;
46#[doc = "Field `se_sha_0_mode` writer - "]
47pub type SE_SHA_0_MODE_W<'a, const O: u8> =
48 crate::FieldWriter<'a, u32, SE_SHA_0_CTRL_SPEC, u8, u8, 3, O>;
49#[doc = "Field `se_sha_0_en` reader - "]
50pub type SE_SHA_0_EN_R = crate::BitReader<bool>;
51#[doc = "Field `se_sha_0_en` writer - "]
52pub type SE_SHA_0_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
53#[doc = "Field `se_sha_0_hash_sel` reader - "]
54pub type SE_SHA_0_HASH_SEL_R = crate::BitReader<bool>;
55#[doc = "Field `se_sha_0_hash_sel` writer - "]
56pub type SE_SHA_0_HASH_SEL_W<'a, const O: u8> =
57 crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
58#[doc = "Field `se_sha_0_int` reader - "]
59pub type SE_SHA_0_INT_R = crate::BitReader<bool>;
60#[doc = "Field `se_sha_0_int_clr_1t` reader - "]
61pub type SE_SHA_0_INT_CLR_1T_R = crate::BitReader<bool>;
62#[doc = "Field `se_sha_0_int_clr_1t` writer - "]
63pub type SE_SHA_0_INT_CLR_1T_W<'a, const O: u8> =
64 crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
65#[doc = "Field `se_sha_0_int_set_1t` reader - "]
66pub type SE_SHA_0_INT_SET_1T_R = crate::BitReader<bool>;
67#[doc = "Field `se_sha_0_int_set_1t` writer - "]
68pub type SE_SHA_0_INT_SET_1T_W<'a, const O: u8> =
69 crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
70#[doc = "Field `se_sha_0_int_mask` reader - "]
71pub type SE_SHA_0_INT_MASK_R = crate::BitReader<bool>;
72#[doc = "Field `se_sha_0_int_mask` writer - "]
73pub type SE_SHA_0_INT_MASK_W<'a, const O: u8> =
74 crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
75#[doc = "Field `se_sha_0_link_mode` reader - "]
76pub type SE_SHA_0_LINK_MODE_R = crate::BitReader<bool>;
77#[doc = "Field `se_sha_0_link_mode` writer - "]
78pub type SE_SHA_0_LINK_MODE_W<'a, const O: u8> =
79 crate::BitWriter<'a, u32, SE_SHA_0_CTRL_SPEC, bool, O>;
80#[doc = "Field `se_sha_0_msg_len` reader - "]
81pub type SE_SHA_0_MSG_LEN_R = crate::FieldReader<u16, u16>;
82#[doc = "Field `se_sha_0_msg_len` writer - "]
83pub type SE_SHA_0_MSG_LEN_W<'a, const O: u8> =
84 crate::FieldWriter<'a, u32, SE_SHA_0_CTRL_SPEC, u16, u16, 16, O>;
85impl R {
86 #[doc = "Bit 0"]
87 #[inline(always)]
88 pub fn se_sha_0_busy(&self) -> SE_SHA_0_BUSY_R {
89 SE_SHA_0_BUSY_R::new((self.bits & 1) != 0)
90 }
91 #[doc = "Bit 1"]
92 #[inline(always)]
93 pub fn se_sha_0_trig_1t(&self) -> SE_SHA_0_TRIG_1T_R {
94 SE_SHA_0_TRIG_1T_R::new(((self.bits >> 1) & 1) != 0)
95 }
96 #[doc = "Bits 2:4"]
97 #[inline(always)]
98 pub fn se_sha_0_mode(&self) -> SE_SHA_0_MODE_R {
99 SE_SHA_0_MODE_R::new(((self.bits >> 2) & 7) as u8)
100 }
101 #[doc = "Bit 5"]
102 #[inline(always)]
103 pub fn se_sha_0_en(&self) -> SE_SHA_0_EN_R {
104 SE_SHA_0_EN_R::new(((self.bits >> 5) & 1) != 0)
105 }
106 #[doc = "Bit 6"]
107 #[inline(always)]
108 pub fn se_sha_0_hash_sel(&self) -> SE_SHA_0_HASH_SEL_R {
109 SE_SHA_0_HASH_SEL_R::new(((self.bits >> 6) & 1) != 0)
110 }
111 #[doc = "Bit 8"]
112 #[inline(always)]
113 pub fn se_sha_0_int(&self) -> SE_SHA_0_INT_R {
114 SE_SHA_0_INT_R::new(((self.bits >> 8) & 1) != 0)
115 }
116 #[doc = "Bit 9"]
117 #[inline(always)]
118 pub fn se_sha_0_int_clr_1t(&self) -> SE_SHA_0_INT_CLR_1T_R {
119 SE_SHA_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
120 }
121 #[doc = "Bit 10"]
122 #[inline(always)]
123 pub fn se_sha_0_int_set_1t(&self) -> SE_SHA_0_INT_SET_1T_R {
124 SE_SHA_0_INT_SET_1T_R::new(((self.bits >> 10) & 1) != 0)
125 }
126 #[doc = "Bit 11"]
127 #[inline(always)]
128 pub fn se_sha_0_int_mask(&self) -> SE_SHA_0_INT_MASK_R {
129 SE_SHA_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
130 }
131 #[doc = "Bit 15"]
132 #[inline(always)]
133 pub fn se_sha_0_link_mode(&self) -> SE_SHA_0_LINK_MODE_R {
134 SE_SHA_0_LINK_MODE_R::new(((self.bits >> 15) & 1) != 0)
135 }
136 #[doc = "Bits 16:31"]
137 #[inline(always)]
138 pub fn se_sha_0_msg_len(&self) -> SE_SHA_0_MSG_LEN_R {
139 SE_SHA_0_MSG_LEN_R::new(((self.bits >> 16) & 0xffff) as u16)
140 }
141}
142impl W {
143 #[doc = "Bit 1"]
144 #[inline(always)]
145 #[must_use]
146 pub fn se_sha_0_trig_1t(&mut self) -> SE_SHA_0_TRIG_1T_W<1> {
147 SE_SHA_0_TRIG_1T_W::new(self)
148 }
149 #[doc = "Bits 2:4"]
150 #[inline(always)]
151 #[must_use]
152 pub fn se_sha_0_mode(&mut self) -> SE_SHA_0_MODE_W<2> {
153 SE_SHA_0_MODE_W::new(self)
154 }
155 #[doc = "Bit 5"]
156 #[inline(always)]
157 #[must_use]
158 pub fn se_sha_0_en(&mut self) -> SE_SHA_0_EN_W<5> {
159 SE_SHA_0_EN_W::new(self)
160 }
161 #[doc = "Bit 6"]
162 #[inline(always)]
163 #[must_use]
164 pub fn se_sha_0_hash_sel(&mut self) -> SE_SHA_0_HASH_SEL_W<6> {
165 SE_SHA_0_HASH_SEL_W::new(self)
166 }
167 #[doc = "Bit 9"]
168 #[inline(always)]
169 #[must_use]
170 pub fn se_sha_0_int_clr_1t(&mut self) -> SE_SHA_0_INT_CLR_1T_W<9> {
171 SE_SHA_0_INT_CLR_1T_W::new(self)
172 }
173 #[doc = "Bit 10"]
174 #[inline(always)]
175 #[must_use]
176 pub fn se_sha_0_int_set_1t(&mut self) -> SE_SHA_0_INT_SET_1T_W<10> {
177 SE_SHA_0_INT_SET_1T_W::new(self)
178 }
179 #[doc = "Bit 11"]
180 #[inline(always)]
181 #[must_use]
182 pub fn se_sha_0_int_mask(&mut self) -> SE_SHA_0_INT_MASK_W<11> {
183 SE_SHA_0_INT_MASK_W::new(self)
184 }
185 #[doc = "Bit 15"]
186 #[inline(always)]
187 #[must_use]
188 pub fn se_sha_0_link_mode(&mut self) -> SE_SHA_0_LINK_MODE_W<15> {
189 SE_SHA_0_LINK_MODE_W::new(self)
190 }
191 #[doc = "Bits 16:31"]
192 #[inline(always)]
193 #[must_use]
194 pub fn se_sha_0_msg_len(&mut self) -> SE_SHA_0_MSG_LEN_W<16> {
195 SE_SHA_0_MSG_LEN_W::new(self)
196 }
197 #[doc = "Writes raw bits to the register."]
198 #[inline(always)]
199 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
200 self.0.bits(bits);
201 self
202 }
203}
204#[doc = "se_sha_0_ctrl.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_sha_0_ctrl](index.html) module"]
205pub struct SE_SHA_0_CTRL_SPEC;
206impl crate::RegisterSpec for SE_SHA_0_CTRL_SPEC {
207 type Ux = u32;
208}
209#[doc = "`read()` method returns [se_sha_0_ctrl::R](R) reader structure"]
210impl crate::Readable for SE_SHA_0_CTRL_SPEC {
211 type Reader = R;
212}
213#[doc = "`write(|w| ..)` method takes [se_sha_0_ctrl::W](W) writer structure"]
214impl crate::Writable for SE_SHA_0_CTRL_SPEC {
215 type Writer = W;
216 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
218}
219#[doc = "`reset()` method sets se_sha_0_ctrl to value 0"]
220impl crate::Resettable for SE_SHA_0_CTRL_SPEC {
221 const RESET_VALUE: Self::Ux = 0;
222}