bl602_pac/sec_eng/
se_pka_0_ctrl_0.rs

1#[doc = "Register `se_pka_0_ctrl_0` reader"]
2pub struct R(crate::R<SE_PKA_0_CTRL_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SE_PKA_0_CTRL_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SE_PKA_0_CTRL_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SE_PKA_0_CTRL_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `se_pka_0_ctrl_0` writer"]
17pub struct W(crate::W<SE_PKA_0_CTRL_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SE_PKA_0_CTRL_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SE_PKA_0_CTRL_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SE_PKA_0_CTRL_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `se_pka_0_done` reader - "]
38pub type SE_PKA_0_DONE_R = crate::BitReader<bool>;
39#[doc = "Field `se_pka_0_done_clr_1t` reader - "]
40pub type SE_PKA_0_DONE_CLR_1T_R = crate::BitReader<bool>;
41#[doc = "Field `se_pka_0_done_clr_1t` writer - "]
42pub type SE_PKA_0_DONE_CLR_1T_W<'a, const O: u8> =
43    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
44#[doc = "Field `se_pka_0_busy` reader - "]
45pub type SE_PKA_0_BUSY_R = crate::BitReader<bool>;
46#[doc = "Field `se_pka_0_en` reader - "]
47pub type SE_PKA_0_EN_R = crate::BitReader<bool>;
48#[doc = "Field `se_pka_0_en` writer - "]
49pub type SE_PKA_0_EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
50#[doc = "Field `se_pka_0_prot_md` reader - "]
51pub type SE_PKA_0_PROT_MD_R = crate::FieldReader<u8, u8>;
52#[doc = "Field `se_pka_0_prot_md` writer - "]
53pub type SE_PKA_0_PROT_MD_W<'a, const O: u8> =
54    crate::FieldWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, u8, u8, 4, O>;
55#[doc = "Field `se_pka_0_int` reader - "]
56pub type SE_PKA_0_INT_R = crate::BitReader<bool>;
57#[doc = "Field `se_pka_0_int_clr_1t` reader - "]
58pub type SE_PKA_0_INT_CLR_1T_R = crate::BitReader<bool>;
59#[doc = "Field `se_pka_0_int_clr_1t` writer - "]
60pub type SE_PKA_0_INT_CLR_1T_W<'a, const O: u8> =
61    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
62#[doc = "Field `se_pka_0_int_set` reader - "]
63pub type SE_PKA_0_INT_SET_R = crate::BitReader<bool>;
64#[doc = "Field `se_pka_0_int_set` writer - "]
65pub type SE_PKA_0_INT_SET_W<'a, const O: u8> =
66    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
67#[doc = "Field `se_pka_0_int_mask` reader - "]
68pub type SE_PKA_0_INT_MASK_R = crate::BitReader<bool>;
69#[doc = "Field `se_pka_0_int_mask` writer - "]
70pub type SE_PKA_0_INT_MASK_W<'a, const O: u8> =
71    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
72#[doc = "Field `se_pka_0_endian` reader - "]
73pub type SE_PKA_0_ENDIAN_R = crate::BitReader<bool>;
74#[doc = "Field `se_pka_0_endian` writer - "]
75pub type SE_PKA_0_ENDIAN_W<'a, const O: u8> =
76    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
77#[doc = "Field `se_pka_0_ram_clr_md` reader - "]
78pub type SE_PKA_0_RAM_CLR_MD_R = crate::BitReader<bool>;
79#[doc = "Field `se_pka_0_ram_clr_md` writer - "]
80pub type SE_PKA_0_RAM_CLR_MD_W<'a, const O: u8> =
81    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
82#[doc = "Field `se_pka_0_status_clr_1t` reader - "]
83pub type SE_PKA_0_STATUS_CLR_1T_R = crate::BitReader<bool>;
84#[doc = "Field `se_pka_0_status_clr_1t` writer - "]
85pub type SE_PKA_0_STATUS_CLR_1T_W<'a, const O: u8> =
86    crate::BitWriter<'a, u32, SE_PKA_0_CTRL_0_SPEC, bool, O>;
87#[doc = "Field `se_pka_0_status` reader - "]
88pub type SE_PKA_0_STATUS_R = crate::FieldReader<u16, u16>;
89impl R {
90    #[doc = "Bit 0"]
91    #[inline(always)]
92    pub fn se_pka_0_done(&self) -> SE_PKA_0_DONE_R {
93        SE_PKA_0_DONE_R::new((self.bits & 1) != 0)
94    }
95    #[doc = "Bit 1"]
96    #[inline(always)]
97    pub fn se_pka_0_done_clr_1t(&self) -> SE_PKA_0_DONE_CLR_1T_R {
98        SE_PKA_0_DONE_CLR_1T_R::new(((self.bits >> 1) & 1) != 0)
99    }
100    #[doc = "Bit 2"]
101    #[inline(always)]
102    pub fn se_pka_0_busy(&self) -> SE_PKA_0_BUSY_R {
103        SE_PKA_0_BUSY_R::new(((self.bits >> 2) & 1) != 0)
104    }
105    #[doc = "Bit 3"]
106    #[inline(always)]
107    pub fn se_pka_0_en(&self) -> SE_PKA_0_EN_R {
108        SE_PKA_0_EN_R::new(((self.bits >> 3) & 1) != 0)
109    }
110    #[doc = "Bits 4:7"]
111    #[inline(always)]
112    pub fn se_pka_0_prot_md(&self) -> SE_PKA_0_PROT_MD_R {
113        SE_PKA_0_PROT_MD_R::new(((self.bits >> 4) & 0x0f) as u8)
114    }
115    #[doc = "Bit 8"]
116    #[inline(always)]
117    pub fn se_pka_0_int(&self) -> SE_PKA_0_INT_R {
118        SE_PKA_0_INT_R::new(((self.bits >> 8) & 1) != 0)
119    }
120    #[doc = "Bit 9"]
121    #[inline(always)]
122    pub fn se_pka_0_int_clr_1t(&self) -> SE_PKA_0_INT_CLR_1T_R {
123        SE_PKA_0_INT_CLR_1T_R::new(((self.bits >> 9) & 1) != 0)
124    }
125    #[doc = "Bit 10"]
126    #[inline(always)]
127    pub fn se_pka_0_int_set(&self) -> SE_PKA_0_INT_SET_R {
128        SE_PKA_0_INT_SET_R::new(((self.bits >> 10) & 1) != 0)
129    }
130    #[doc = "Bit 11"]
131    #[inline(always)]
132    pub fn se_pka_0_int_mask(&self) -> SE_PKA_0_INT_MASK_R {
133        SE_PKA_0_INT_MASK_R::new(((self.bits >> 11) & 1) != 0)
134    }
135    #[doc = "Bit 12"]
136    #[inline(always)]
137    pub fn se_pka_0_endian(&self) -> SE_PKA_0_ENDIAN_R {
138        SE_PKA_0_ENDIAN_R::new(((self.bits >> 12) & 1) != 0)
139    }
140    #[doc = "Bit 13"]
141    #[inline(always)]
142    pub fn se_pka_0_ram_clr_md(&self) -> SE_PKA_0_RAM_CLR_MD_R {
143        SE_PKA_0_RAM_CLR_MD_R::new(((self.bits >> 13) & 1) != 0)
144    }
145    #[doc = "Bit 16"]
146    #[inline(always)]
147    pub fn se_pka_0_status_clr_1t(&self) -> SE_PKA_0_STATUS_CLR_1T_R {
148        SE_PKA_0_STATUS_CLR_1T_R::new(((self.bits >> 16) & 1) != 0)
149    }
150    #[doc = "Bits 17:31"]
151    #[inline(always)]
152    pub fn se_pka_0_status(&self) -> SE_PKA_0_STATUS_R {
153        SE_PKA_0_STATUS_R::new(((self.bits >> 17) & 0x7fff) as u16)
154    }
155}
156impl W {
157    #[doc = "Bit 1"]
158    #[inline(always)]
159    #[must_use]
160    pub fn se_pka_0_done_clr_1t(&mut self) -> SE_PKA_0_DONE_CLR_1T_W<1> {
161        SE_PKA_0_DONE_CLR_1T_W::new(self)
162    }
163    #[doc = "Bit 3"]
164    #[inline(always)]
165    #[must_use]
166    pub fn se_pka_0_en(&mut self) -> SE_PKA_0_EN_W<3> {
167        SE_PKA_0_EN_W::new(self)
168    }
169    #[doc = "Bits 4:7"]
170    #[inline(always)]
171    #[must_use]
172    pub fn se_pka_0_prot_md(&mut self) -> SE_PKA_0_PROT_MD_W<4> {
173        SE_PKA_0_PROT_MD_W::new(self)
174    }
175    #[doc = "Bit 9"]
176    #[inline(always)]
177    #[must_use]
178    pub fn se_pka_0_int_clr_1t(&mut self) -> SE_PKA_0_INT_CLR_1T_W<9> {
179        SE_PKA_0_INT_CLR_1T_W::new(self)
180    }
181    #[doc = "Bit 10"]
182    #[inline(always)]
183    #[must_use]
184    pub fn se_pka_0_int_set(&mut self) -> SE_PKA_0_INT_SET_W<10> {
185        SE_PKA_0_INT_SET_W::new(self)
186    }
187    #[doc = "Bit 11"]
188    #[inline(always)]
189    #[must_use]
190    pub fn se_pka_0_int_mask(&mut self) -> SE_PKA_0_INT_MASK_W<11> {
191        SE_PKA_0_INT_MASK_W::new(self)
192    }
193    #[doc = "Bit 12"]
194    #[inline(always)]
195    #[must_use]
196    pub fn se_pka_0_endian(&mut self) -> SE_PKA_0_ENDIAN_W<12> {
197        SE_PKA_0_ENDIAN_W::new(self)
198    }
199    #[doc = "Bit 13"]
200    #[inline(always)]
201    #[must_use]
202    pub fn se_pka_0_ram_clr_md(&mut self) -> SE_PKA_0_RAM_CLR_MD_W<13> {
203        SE_PKA_0_RAM_CLR_MD_W::new(self)
204    }
205    #[doc = "Bit 16"]
206    #[inline(always)]
207    #[must_use]
208    pub fn se_pka_0_status_clr_1t(&mut self) -> SE_PKA_0_STATUS_CLR_1T_W<16> {
209        SE_PKA_0_STATUS_CLR_1T_W::new(self)
210    }
211    #[doc = "Writes raw bits to the register."]
212    #[inline(always)]
213    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
214        self.0.bits(bits);
215        self
216    }
217}
218#[doc = "se_pka_0_ctrl_0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [se_pka_0_ctrl_0](index.html) module"]
219pub struct SE_PKA_0_CTRL_0_SPEC;
220impl crate::RegisterSpec for SE_PKA_0_CTRL_0_SPEC {
221    type Ux = u32;
222}
223#[doc = "`read()` method returns [se_pka_0_ctrl_0::R](R) reader structure"]
224impl crate::Readable for SE_PKA_0_CTRL_0_SPEC {
225    type Reader = R;
226}
227#[doc = "`write(|w| ..)` method takes [se_pka_0_ctrl_0::W](W) writer structure"]
228impl crate::Writable for SE_PKA_0_CTRL_0_SPEC {
229    type Writer = W;
230    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
231    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
232}
233#[doc = "`reset()` method sets se_pka_0_ctrl_0 to value 0"]
234impl crate::Resettable for SE_PKA_0_CTRL_0_SPEC {
235    const RESET_VALUE: Self::Ux = 0;
236}
bl602_pac/sec_eng/se_pka_0_ctrl_0.rs

bl602_pac/sec_eng/
se_pka_0_ctrl_0.rs
