1#[doc = "Register `sdm1` reader"]
2pub struct R(crate::R<SDM1_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SDM1_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SDM1_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SDM1_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `sdm1` writer"]
17pub struct W(crate::W<SDM1_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SDM1_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SDM1_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SDM1_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `lo_sdm_dither_sel_hw` reader - "]
38pub type LO_SDM_DITHER_SEL_HW_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `lo_sdm_dither_sel_hw` writer - "]
40pub type LO_SDM_DITHER_SEL_HW_W<'a, const O: u8> =
41 crate::FieldWriter<'a, u32, SDM1_SPEC, u8, u8, 2, O>;
42#[doc = "Field `lo_sdm_bypass_hw` reader - "]
43pub type LO_SDM_BYPASS_HW_R = crate::BitReader<bool>;
44#[doc = "Field `lo_sdm_bypass_hw` writer - "]
45pub type LO_SDM_BYPASS_HW_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDM1_SPEC, bool, O>;
46#[doc = "Field `lo_sdm_dither_sel` reader - "]
47pub type LO_SDM_DITHER_SEL_R = crate::FieldReader<u8, u8>;
48#[doc = "Field `lo_sdm_dither_sel` writer - "]
49pub type LO_SDM_DITHER_SEL_W<'a, const O: u8> =
50 crate::FieldWriter<'a, u32, SDM1_SPEC, u8, u8, 2, O>;
51#[doc = "Field `lo_sdm_bypass` reader - "]
52pub type LO_SDM_BYPASS_R = crate::BitReader<bool>;
53#[doc = "Field `lo_sdm_bypass` writer - "]
54pub type LO_SDM_BYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDM1_SPEC, bool, O>;
55#[doc = "Field `lo_sdm_rstb` reader - "]
56pub type LO_SDM_RSTB_R = crate::BitReader<bool>;
57#[doc = "Field `lo_sdm_rstb` writer - "]
58pub type LO_SDM_RSTB_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDM1_SPEC, bool, O>;
59#[doc = "Field `lo_sdm_rstb_hw` reader - "]
60pub type LO_SDM_RSTB_HW_R = crate::BitReader<bool>;
61#[doc = "Field `lo_sdm_rstb_hw` writer - "]
62pub type LO_SDM_RSTB_HW_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDM1_SPEC, bool, O>;
63#[doc = "Field `lo_sdm_flag` reader - "]
64pub type LO_SDM_FLAG_R = crate::BitReader<bool>;
65#[doc = "Field `lo_sdm_flag` writer - "]
66pub type LO_SDM_FLAG_W<'a, const O: u8> = crate::BitWriter<'a, u32, SDM1_SPEC, bool, O>;
67impl R {
68 #[doc = "Bits 0:1"]
69 #[inline(always)]
70 pub fn lo_sdm_dither_sel_hw(&self) -> LO_SDM_DITHER_SEL_HW_R {
71 LO_SDM_DITHER_SEL_HW_R::new((self.bits & 3) as u8)
72 }
73 #[doc = "Bit 4"]
74 #[inline(always)]
75 pub fn lo_sdm_bypass_hw(&self) -> LO_SDM_BYPASS_HW_R {
76 LO_SDM_BYPASS_HW_R::new(((self.bits >> 4) & 1) != 0)
77 }
78 #[doc = "Bits 8:9"]
79 #[inline(always)]
80 pub fn lo_sdm_dither_sel(&self) -> LO_SDM_DITHER_SEL_R {
81 LO_SDM_DITHER_SEL_R::new(((self.bits >> 8) & 3) as u8)
82 }
83 #[doc = "Bit 12"]
84 #[inline(always)]
85 pub fn lo_sdm_bypass(&self) -> LO_SDM_BYPASS_R {
86 LO_SDM_BYPASS_R::new(((self.bits >> 12) & 1) != 0)
87 }
88 #[doc = "Bit 16"]
89 #[inline(always)]
90 pub fn lo_sdm_rstb(&self) -> LO_SDM_RSTB_R {
91 LO_SDM_RSTB_R::new(((self.bits >> 16) & 1) != 0)
92 }
93 #[doc = "Bit 17"]
94 #[inline(always)]
95 pub fn lo_sdm_rstb_hw(&self) -> LO_SDM_RSTB_HW_R {
96 LO_SDM_RSTB_HW_R::new(((self.bits >> 17) & 1) != 0)
97 }
98 #[doc = "Bit 20"]
99 #[inline(always)]
100 pub fn lo_sdm_flag(&self) -> LO_SDM_FLAG_R {
101 LO_SDM_FLAG_R::new(((self.bits >> 20) & 1) != 0)
102 }
103}
104impl W {
105 #[doc = "Bits 0:1"]
106 #[inline(always)]
107 #[must_use]
108 pub fn lo_sdm_dither_sel_hw(&mut self) -> LO_SDM_DITHER_SEL_HW_W<0> {
109 LO_SDM_DITHER_SEL_HW_W::new(self)
110 }
111 #[doc = "Bit 4"]
112 #[inline(always)]
113 #[must_use]
114 pub fn lo_sdm_bypass_hw(&mut self) -> LO_SDM_BYPASS_HW_W<4> {
115 LO_SDM_BYPASS_HW_W::new(self)
116 }
117 #[doc = "Bits 8:9"]
118 #[inline(always)]
119 #[must_use]
120 pub fn lo_sdm_dither_sel(&mut self) -> LO_SDM_DITHER_SEL_W<8> {
121 LO_SDM_DITHER_SEL_W::new(self)
122 }
123 #[doc = "Bit 12"]
124 #[inline(always)]
125 #[must_use]
126 pub fn lo_sdm_bypass(&mut self) -> LO_SDM_BYPASS_W<12> {
127 LO_SDM_BYPASS_W::new(self)
128 }
129 #[doc = "Bit 16"]
130 #[inline(always)]
131 #[must_use]
132 pub fn lo_sdm_rstb(&mut self) -> LO_SDM_RSTB_W<16> {
133 LO_SDM_RSTB_W::new(self)
134 }
135 #[doc = "Bit 17"]
136 #[inline(always)]
137 #[must_use]
138 pub fn lo_sdm_rstb_hw(&mut self) -> LO_SDM_RSTB_HW_W<17> {
139 LO_SDM_RSTB_HW_W::new(self)
140 }
141 #[doc = "Bit 20"]
142 #[inline(always)]
143 #[must_use]
144 pub fn lo_sdm_flag(&mut self) -> LO_SDM_FLAG_W<20> {
145 LO_SDM_FLAG_W::new(self)
146 }
147 #[doc = "Writes raw bits to the register."]
148 #[inline(always)]
149 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
150 self.0.bits(bits);
151 self
152 }
153}
154#[doc = "sdm1.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdm1](index.html) module"]
155pub struct SDM1_SPEC;
156impl crate::RegisterSpec for SDM1_SPEC {
157 type Ux = u32;
158}
159#[doc = "`read()` method returns [sdm1::R](R) reader structure"]
160impl crate::Readable for SDM1_SPEC {
161 type Reader = R;
162}
163#[doc = "`write(|w| ..)` method takes [sdm1::W](W) writer structure"]
164impl crate::Writable for SDM1_SPEC {
165 type Writer = W;
166 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
167 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
168}
169#[doc = "`reset()` method sets sdm1 to value 0"]
170impl crate::Resettable for SDM1_SPEC {
171 const RESET_VALUE: Self::Ux = 0;
172}