bl602_pac/rf/
rf_sram_ctrl0.rs

1#[doc = "Register `rf_sram_ctrl0` reader"]
2pub struct R(crate::R<RF_SRAM_CTRL0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RF_SRAM_CTRL0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RF_SRAM_CTRL0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RF_SRAM_CTRL0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `rf_sram_ctrl0` writer"]
17pub struct W(crate::W<RF_SRAM_CTRL0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RF_SRAM_CTRL0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RF_SRAM_CTRL0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RF_SRAM_CTRL0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `rf_sram_link_dly` reader - "]
38pub type RF_SRAM_LINK_DLY_R = crate::FieldReader<u16, u16>;
39#[doc = "Field `rf_sram_link_dly` writer - "]
40pub type RF_SRAM_LINK_DLY_W<'a, const O: u8> =
41    crate::FieldWriter<'a, u32, RF_SRAM_CTRL0_SPEC, u16, u16, 16, O>;
42#[doc = "Field `rf_sram_link_mode` reader - "]
43pub type RF_SRAM_LINK_MODE_R = crate::FieldReader<u8, u8>;
44#[doc = "Field `rf_sram_link_mode` writer - "]
45pub type RF_SRAM_LINK_MODE_W<'a, const O: u8> =
46    crate::FieldWriter<'a, u32, RF_SRAM_CTRL0_SPEC, u8, u8, 2, O>;
47#[doc = "Field `rf_sram_swap` reader - "]
48pub type RF_SRAM_SWAP_R = crate::BitReader<bool>;
49#[doc = "Field `rf_sram_swap` writer - "]
50pub type RF_SRAM_SWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, RF_SRAM_CTRL0_SPEC, bool, O>;
51#[doc = "Field `rf_sram_ext_clr` reader - "]
52pub type RF_SRAM_EXT_CLR_R = crate::BitReader<bool>;
53#[doc = "Field `rf_sram_ext_clr` writer - "]
54pub type RF_SRAM_EXT_CLR_W<'a, const O: u8> =
55    crate::BitWriter<'a, u32, RF_SRAM_CTRL0_SPEC, bool, O>;
56impl R {
57    #[doc = "Bits 0:15"]
58    #[inline(always)]
59    pub fn rf_sram_link_dly(&self) -> RF_SRAM_LINK_DLY_R {
60        RF_SRAM_LINK_DLY_R::new((self.bits & 0xffff) as u16)
61    }
62    #[doc = "Bits 16:17"]
63    #[inline(always)]
64    pub fn rf_sram_link_mode(&self) -> RF_SRAM_LINK_MODE_R {
65        RF_SRAM_LINK_MODE_R::new(((self.bits >> 16) & 3) as u8)
66    }
67    #[doc = "Bit 18"]
68    #[inline(always)]
69    pub fn rf_sram_swap(&self) -> RF_SRAM_SWAP_R {
70        RF_SRAM_SWAP_R::new(((self.bits >> 18) & 1) != 0)
71    }
72    #[doc = "Bit 19"]
73    #[inline(always)]
74    pub fn rf_sram_ext_clr(&self) -> RF_SRAM_EXT_CLR_R {
75        RF_SRAM_EXT_CLR_R::new(((self.bits >> 19) & 1) != 0)
76    }
77}
78impl W {
79    #[doc = "Bits 0:15"]
80    #[inline(always)]
81    #[must_use]
82    pub fn rf_sram_link_dly(&mut self) -> RF_SRAM_LINK_DLY_W<0> {
83        RF_SRAM_LINK_DLY_W::new(self)
84    }
85    #[doc = "Bits 16:17"]
86    #[inline(always)]
87    #[must_use]
88    pub fn rf_sram_link_mode(&mut self) -> RF_SRAM_LINK_MODE_W<16> {
89        RF_SRAM_LINK_MODE_W::new(self)
90    }
91    #[doc = "Bit 18"]
92    #[inline(always)]
93    #[must_use]
94    pub fn rf_sram_swap(&mut self) -> RF_SRAM_SWAP_W<18> {
95        RF_SRAM_SWAP_W::new(self)
96    }
97    #[doc = "Bit 19"]
98    #[inline(always)]
99    #[must_use]
100    pub fn rf_sram_ext_clr(&mut self) -> RF_SRAM_EXT_CLR_W<19> {
101        RF_SRAM_EXT_CLR_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "rf_sram_ctrl0.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rf_sram_ctrl0](index.html) module"]
111pub struct RF_SRAM_CTRL0_SPEC;
112impl crate::RegisterSpec for RF_SRAM_CTRL0_SPEC {
113    type Ux = u32;
114}
115#[doc = "`read()` method returns [rf_sram_ctrl0::R](R) reader structure"]
116impl crate::Readable for RF_SRAM_CTRL0_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [rf_sram_ctrl0::W](W) writer structure"]
120impl crate::Writable for RF_SRAM_CTRL0_SPEC {
121    type Writer = W;
122    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124}
125#[doc = "`reset()` method sets rf_sram_ctrl0 to value 0"]
126impl crate::Resettable for RF_SRAM_CTRL0_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
bl602_pac/rf/rf_sram_ctrl0.rs

bl602_pac/rf/
rf_sram_ctrl0.rs
